diff options
| -rw-r--r-- | llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp | 16 | ||||
| -rw-r--r-- | llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp | 13 |
2 files changed, 22 insertions, 7 deletions
diff --git a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp index c57696979d5..110053829a6 100644 --- a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp +++ b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp @@ -208,13 +208,17 @@ static void randomize(const Variable &Var, llvm::MCOperand &AssignedValue) { static void setRegisterOperandValue(const RegisterOperandAssignment &ROV, InstructionInstance &II) { assert(ROV.Op); - assert(ROV.Op->IsExplicit); - auto &AssignedValue = II.getValueFor(*ROV.Op); - if (AssignedValue.isValid()) { - assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg); - return; + if (ROV.Op->IsExplicit) { + auto &AssignedValue = II.getValueFor(*ROV.Op); + if (AssignedValue.isValid()) { + assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg); + return; + } + AssignedValue = llvm::MCOperand::createReg(ROV.Reg); + } else { + assert(ROV.Op->ImplicitReg != nullptr); + assert(ROV.Reg == *ROV.Op->ImplicitReg); } - AssignedValue = llvm::MCOperand::createReg(ROV.Reg); } size_t randomBit(const llvm::BitVector &Vector) { diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp index 0e4a3fb8f17..d020d4cf309 100644 --- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp @@ -103,11 +103,22 @@ TEST_F(LatencySnippetGeneratorTest, DependencyThroughOtherOpcode) { const unsigned Opcode = llvm::X86::CMP64rr; auto Conf = checkAndGetConfiguration(Opcode); - EXPECT_THAT(Conf.Info, testing::HasSubstr("cycle through CMOVLE16rr")); + EXPECT_THAT(Conf.Info, testing::HasSubstr("cycle through")); ASSERT_THAT(Conf.Snippet, testing::SizeIs(2)); + const llvm::MCInst Instr = Conf.Snippet[0]; + EXPECT_THAT(Instr.getOpcode(), Opcode); // TODO: check that the two instructions alias each other. } +TEST_F(LatencySnippetGeneratorTest, LAHF) { + const unsigned Opcode = llvm::X86::LAHF; + auto Conf = checkAndGetConfiguration(Opcode); + EXPECT_THAT(Conf.Info, testing::HasSubstr("cycle through")); + ASSERT_THAT(Conf.Snippet, testing::SizeIs(2)); + const llvm::MCInst Instr = Conf.Snippet[0]; + EXPECT_THAT(Instr.getOpcode(), Opcode); +} + class UopsSnippetGeneratorTest : public X86SnippetGeneratorTest { protected: UopsSnippetGeneratorTest() : Runner(State) {} |
