diff options
| -rw-r--r-- | llvm/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir | 60 | ||||
| -rw-r--r-- | llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir | 54 |
2 files changed, 57 insertions, 57 deletions
diff --git a/llvm/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir b/llvm/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir index efebdf7ce57..b5c4c47f9e3 100644 --- a/llvm/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir +++ b/llvm/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir @@ -3,9 +3,9 @@ ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll' target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv7" - + %struct.s = type opaque - + ; Function Attrs: nounwind define arm_aapcscc i32 @f(%struct.s* %s, i32 %u, i8* %b, i32 %n) #0 !dbg !4 { entry: @@ -15,30 +15,30 @@ tail call void @llvm.dbg.value(metadata i32 %n, i64 0, metadata !21, metadata !27), !dbg !28 %cmp = icmp ult i32 %n, 4, !dbg !29 br i1 %cmp, label %return, label %if.end, !dbg !31 - + if.end: ; preds = %entry tail call arm_aapcscc void @g(%struct.s* %s, i8* %b, i32 %n) #3, !dbg !32 br label %return, !dbg !33 - + return: ; preds = %if.end, %entry %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ] ret i32 %retval.0, !dbg !34 } - + declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1 - + ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 - + attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind readnone } attributes #3 = { nounwind } - + !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!22, !23, !24, !25} !llvm.ident = !{!26} - + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "<stdin>", directory: "/Users/compnerd/Source/llvm") !2 = !{} @@ -84,25 +84,25 @@ allVRegsAllocated: true isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false -liveins: +liveins: - { reg: '%r0' } - { reg: '%r2' } - { reg: '%r3' } -calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', - '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', - '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', - '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', - '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', - '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', - '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', - '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', - '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', - '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', - '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', - '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', - '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', +calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', + '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', + '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', + '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', + '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', + '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', + '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', + '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', + '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', + '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', + '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', + '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', + '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', '%d11_d12_d13_d14' ] -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -116,32 +116,32 @@ frameInfo: hasOpaqueSPAdjustment: false hasVAStart: false hasMustTailInVarArgFunc: false -stack: +stack: - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' } - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' } body: | bb.0.entry: successors: %bb.1, %bb.2.if.end liveins: %r0, %r2, %r3, %lr, %r7 - + DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31 t2Bcc %bb.2.if.end, 2, killed %cpsr - + bb.1: liveins: %lr, %r7 - + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 %r0 = t2MOVi -1, 14, _, _ DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 tBX_RET 14, _, implicit %r0, debug-location !34 - + bb.2.if.end: liveins: %r0, %r2, %r3, %r7, %lr - + %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 8 frame-setup CFI_INSTRUCTION .cfi_offset %lr, -4 diff --git a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir index 44d370908e9..ae7a6350170 100644 --- a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir +++ b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir @@ -3,9 +3,9 @@ ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll' target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv7" - + %struct.s = type opaque - + ; Function Attrs: nounwind define arm_aapcscc i32 @f(%struct.s* %s, i32 %u, i8* %b, i32 %n) #0 !dbg !4 { entry: @@ -15,11 +15,11 @@ tail call void @llvm.dbg.value(metadata i32 %n, i64 0, metadata !21, metadata !27), !dbg !28 %cmp = icmp ult i32 %n, 4, !dbg !29 br i1 %cmp, label %return, label %if.end, !dbg !31 - + if.end: ; preds = %entry tail call arm_aapcscc void @g(%struct.s* %s, i8* %b, i32 %n) #3, !dbg !32 br label %return, !dbg !33 - + return: ; preds = %if.end, %entry %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ] ret i32 %retval.0, !dbg !34 @@ -31,25 +31,25 @@ ; attempts to schedule the Machine Instr, and tries to tag the register in the ; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or ; hopefully, triggering an assert). - + ; CHECK: BUNDLE %ITSTATE<imp-def,dead> ; CHECK: * DBG_VALUE %R1, %noreg, !"u" ; CHECK-NOT: * DBG_VALUE %R1<kill>, %noreg, !"u" - + declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1 - + ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 - + attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind readnone } attributes #3 = { nounwind } - + !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!22, !23, !24, !25} !llvm.ident = !{!26} - + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "<stdin>", directory: "/Users/compnerd/Source/llvm") !2 = !{} @@ -95,25 +95,25 @@ allVRegsAllocated: true isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false -liveins: +liveins: - { reg: '%r0' } - { reg: '%r2' } - { reg: '%r3' } -calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', - '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', - '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', - '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', - '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', - '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', - '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', - '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', - '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', - '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', - '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', - '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', - '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', +calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', + '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', + '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', + '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', + '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', + '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', + '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', + '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', + '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', + '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', + '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', + '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', + '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', '%d11_d12_d13_d14' ] -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -127,13 +127,13 @@ frameInfo: hasOpaqueSPAdjustment: false hasVAStart: false hasMustTailInVarArgFunc: false -stack: +stack: - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' } - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' } body: | bb.0.entry: liveins: %r0, %r2, %r3, %lr, %r7 - + DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 |
