diff options
| -rw-r--r-- | llvm/test/TableGen/RegisterBankEmitter.td | 15 | ||||
| -rw-r--r-- | llvm/utils/TableGen/RegisterBankEmitter.cpp | 14 |
2 files changed, 26 insertions, 3 deletions
diff --git a/llvm/test/TableGen/RegisterBankEmitter.td b/llvm/test/TableGen/RegisterBankEmitter.td new file mode 100644 index 00000000000..88c7ec1f791 --- /dev/null +++ b/llvm/test/TableGen/RegisterBankEmitter.td @@ -0,0 +1,15 @@ +// RUN: llvm-tblgen -gen-register-bank -I %p/../../include %s | FileCheck %s + +include "llvm/Target/Target.td" + +def MyTarget : Target; +def R0 : Register<"r0">; +let Size = 32 in { + def ClassA : RegisterClass<"MyTarget", [i32], 32, (add R0)>; + def ClassB : RegisterClass<"MyTarget", [i1], 32, (add ClassA)>; +} + +// CHECK: GPRRegBankCoverageData +// CHECK: MyTarget::ClassARegClassID +// CHECK: MyTarget::ClassBRegClassID +def GPRRegBank : RegisterBank<"GPR", [ClassA]>; diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp index 816fc3e0a17..bf066412b28 100644 --- a/llvm/utils/TableGen/RegisterBankEmitter.cpp +++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp @@ -168,7 +168,14 @@ void RegisterBankEmitter::emitBaseClassDefinition( static void visitRegisterBankClasses( CodeGenRegBank &RegisterClassHierarchy, const CodeGenRegisterClass *RC, const Twine Kind, - std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn) { + std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn, + SmallPtrSetImpl<const CodeGenRegisterClass *> &VisitedRCs) { + + // Make sure we only visit each class once to avoid infinite loops. + if (VisitedRCs.count(RC)) + return; + VisitedRCs.insert(RC); + // Visit each explicitly named class. VisitFn(RC, Kind.str()); @@ -180,7 +187,7 @@ static void visitRegisterBankClasses( if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass)) visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass, TmpKind + " " + RC->getName() + " subclass", - VisitFn); + VisitFn, VisitedRCs); // Visit each class that contains only subregisters of RC with a common // subregister-index. @@ -273,6 +280,7 @@ void RegisterBankEmitter::run(raw_ostream &OS) { std::vector<RegisterBank> Banks; for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) { + SmallPtrSet<const CodeGenRegisterClass *, 8> VisitedRCs; RegisterBank Bank(*V); for (const CodeGenRegisterClass *RC : @@ -282,7 +290,7 @@ void RegisterBankEmitter::run(raw_ostream &OS) { [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) { DEBUG(dbgs() << "Added " << RC->getName() << "(" << Kind << ")\n"); Bank.addRegisterClass(RC); - }); + }, VisitedRCs); } Banks.push_back(Bank); |
