diff options
| -rw-r--r-- | llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/NVPTX/arithmetic-int.ll | 24 |
2 files changed, 28 insertions, 0 deletions
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index be735f6c1bc..fc9f43af580 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -273,6 +273,10 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM, // PTX does not directly support SELP of i1, so promote to i32 first setOperationAction(ISD::SELECT, MVT::i1, Custom); + // PTX cannot multiply two i64s in a single instruction. + setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); + setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); + // We have some custom DAG combine patterns for these nodes setTargetDAGCombine(ISD::ADD); setTargetDAGCombine(ISD::AND); diff --git a/llvm/test/CodeGen/NVPTX/arithmetic-int.ll b/llvm/test/CodeGen/NVPTX/arithmetic-int.ll index b5a2872299b..e7c968c4c0b 100644 --- a/llvm/test/CodeGen/NVPTX/arithmetic-int.ll +++ b/llvm/test/CodeGen/NVPTX/arithmetic-int.ll @@ -29,6 +29,30 @@ define i64 @mul_i64(i64 %a, i64 %b) { ret i64 %ret } +define i64 @umul_lohi_i64(i64 %a) { +; CHECK-LABEL: umul_lohi_i64( +entry: + %0 = zext i64 %a to i128 + %1 = mul i128 %0, 288 +; CHECK: mul.lo.{{u|s}}64 +; CHECK: mul.hi.{{u|s}}64 + %2 = lshr i128 %1, 1 + %3 = trunc i128 %2 to i64 + ret i64 %3 +} + +define i64 @smul_lohi_i64(i64 %a) { +; CHECK-LABEL: smul_lohi_i64( +entry: + %0 = sext i64 %a to i128 + %1 = mul i128 %0, 288 +; CHECK: mul.lo.{{u|s}}64 +; CHECK: mul.hi.{{u|s}}64 + %2 = ashr i128 %1, 1 + %3 = trunc i128 %2 to i64 + ret i64 %3 +} + define i64 @sdiv_i64(i64 %a, i64 %b) { ; CHECK: div.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}} ; CHECK: ret |
