summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--llvm/lib/Target/AArch64/AArch64FastISel.cpp13
-rw-r--r--llvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll8
-rw-r--r--llvm/test/CodeGen/AArch64/arm64-fast-isel-select.ll12
3 files changed, 15 insertions, 18 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
index 5114acaec41..78b46b8f8d3 100644
--- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
@@ -903,8 +903,7 @@ bool AArch64FastISel::SelectBranch(const Instruction *I) {
.addReg(CondReg)
.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
- TII.get(AArch64::SUBSWri))
- .addReg(ANDReg)
+ TII.get(AArch64::SUBSWri), AArch64::WZR)
.addReg(ANDReg)
.addImm(0)
.addImm(0);
@@ -1110,14 +1109,12 @@ bool AArch64FastISel::EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt) {
if (isICmp) {
if (UseImm)
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
- .addReg(ZReg)
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), ZReg)
.addReg(SrcReg1)
.addImm(Imm)
.addImm(0);
else
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
- .addReg(ZReg)
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), ZReg)
.addReg(SrcReg1)
.addReg(SrcReg2);
} else {
@@ -1197,8 +1194,8 @@ bool AArch64FastISel::SelectSelect(const Instruction *I) {
.addReg(CondReg, getKillRegState(CondIsKill))
.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri))
- .addReg(ANDReg)
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri),
+ AArch64::WZR)
.addReg(ANDReg)
.addImm(0)
.addImm(0);
diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll
index 37a8295c893..7885a6251b8 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll
@@ -95,7 +95,7 @@ entry:
store i64 %d, i64* %d.addr, align 8
%0 = load i16* %b.addr, align 2
; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
+; CHECK: cmp w0, #0
; CHECK: b.eq LBB4_2
%conv = trunc i16 %0 to i1
br i1 %conv, label %if.then, label %if.end
@@ -107,7 +107,7 @@ if.then: ; preds = %entry
if.end: ; preds = %if.then, %entry
%1 = load i32* %c.addr, align 4
; CHECK: and w[[REG:[0-9]+]], w{{[0-9]+}}, #0x1
-; CHECK: subs w{{[0-9]+}}, w[[REG]], #0
+; CHECK: cmp w[[REG]], #0
; CHECK: b.eq LBB4_4
%conv1 = trunc i32 %1 to i1
br i1 %conv1, label %if.then3, label %if.end4
@@ -118,7 +118,7 @@ if.then3: ; preds = %if.end
if.end4: ; preds = %if.then3, %if.end
%2 = load i64* %d.addr, align 8
-; CHECK: subs w{{[0-9]+}}, w{{[0-9]+}}, #0
+; CHECK: cmp w{{[0-9]+}}, #0
; CHECK: b.eq LBB4_6
%conv5 = trunc i64 %2 to i1
br i1 %conv5, label %if.then7, label %if.end8
@@ -141,7 +141,7 @@ define i32 @trunc64(i64 %foo) nounwind {
; CHECK: and [[REG2:x[0-9]+]], x0, [[REG]]
; CHECK: mov x[[REG3:[0-9]+]], [[REG2]]
; CHECK: and [[REG4:w[0-9]+]], w[[REG3]], #0x1
-; CHECK: subs {{w[0-9]+}}, [[REG4]], #0
+; CHECK: cmp [[REG4]], #0
; CHECK: b.eq LBB5_2
%a = and i64 %foo, 1
%b = trunc i64 %a to i1
diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-select.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel-select.ll
index 1cc207f5915..c8a997e9a81 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fast-isel-select.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-select.ll
@@ -4,7 +4,7 @@ define i32 @t1(i32 %c) nounwind readnone {
entry:
; CHECK: @t1
; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
+; CHECK: cmp w0, #0
; CHECK: csel w0, w{{[0-9]+}}, w{{[0-9]+}}, ne
%0 = icmp sgt i32 %c, 1
%1 = select i1 %0, i32 123, i32 357
@@ -15,7 +15,7 @@ define i64 @t2(i32 %c) nounwind readnone {
entry:
; CHECK: @t2
; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
+; CHECK: cmp w0, #0
; CHECK: csel x0, x{{[0-9]+}}, x{{[0-9]+}}, ne
%0 = icmp sgt i32 %c, 1
%1 = select i1 %0, i64 123, i64 357
@@ -26,7 +26,7 @@ define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone {
entry:
; CHECK: @t3
; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
+; CHECK: cmp w0, #0
; CHECK: csel w0, w{{[0-9]+}}, w{{[0-9]+}}, ne
%0 = select i1 %c, i32 %a, i32 %b
ret i32 %0
@@ -36,7 +36,7 @@ define i64 @t4(i1 %c, i64 %a, i64 %b) nounwind readnone {
entry:
; CHECK: @t4
; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
+; CHECK: cmp w0, #0
; CHECK: csel x0, x{{[0-9]+}}, x{{[0-9]+}}, ne
%0 = select i1 %c, i64 %a, i64 %b
ret i64 %0
@@ -46,7 +46,7 @@ define float @t5(i1 %c, float %a, float %b) nounwind readnone {
entry:
; CHECK: @t5
; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
+; CHECK: cmp w0, #0
; CHECK: fcsel s0, s0, s1, ne
%0 = select i1 %c, float %a, float %b
ret float %0
@@ -56,7 +56,7 @@ define double @t6(i1 %c, double %a, double %b) nounwind readnone {
entry:
; CHECK: @t6
; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
+; CHECK: cmp w0, #0
; CHECK: fcsel d0, d0, d1, ne
%0 = select i1 %c, double %a, double %b
ret double %0
OpenPOWER on IntegriCloud