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-rw-r--r--llvm/include/llvm/CodeGen/MIRYamlMapping.h10
-rw-r--r--llvm/lib/CodeGen/MIRParser/MIRParser.cpp19
-rw-r--r--llvm/lib/CodeGen/MIRPrinter.cpp10
-rw-r--r--llvm/test/CodeGen/MIR/machine-function.mir8
-rw-r--r--llvm/test/CodeGen/MIR/register-info.mir36
5 files changed, 79 insertions, 4 deletions
diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
index 4325fb98078..891a01ecb48 100644
--- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
@@ -97,6 +97,13 @@ struct MachineFunction {
unsigned Alignment = 0;
bool ExposesReturnsTwice = false;
bool HasInlineAsm = false;
+ // Register information
+ bool IsSSA = false;
+ bool TracksRegLiveness = false;
+ bool TracksSubRegLiveness = false;
+ // TODO: Serialize virtual register definitions.
+ // TODO: Serialize the various register masks.
+ // TODO: Serialize live in registers.
std::vector<MachineBasicBlock> BasicBlocks;
};
@@ -107,6 +114,9 @@ template <> struct MappingTraits<MachineFunction> {
YamlIO.mapOptional("alignment", MF.Alignment);
YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm);
+ YamlIO.mapOptional("isSSA", MF.IsSSA);
+ YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
+ YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
YamlIO.mapOptional("body", MF.BasicBlocks);
}
};
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 57ecacf7dce..1803116b417 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -19,6 +19,7 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/AsmParser/Parser.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DiagnosticInfo.h"
@@ -83,6 +84,9 @@ public:
bool initializeMachineBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
const yaml::MachineBasicBlock &YamlMBB);
+ bool initializeRegisterInfo(MachineRegisterInfo &RegInfo,
+ const yaml::MachineFunction &YamlMF);
+
private:
/// Return a MIR diagnostic converted from an MI string diagnostic.
SMDiagnostic diagFromMIStringDiag(const SMDiagnostic &Error,
@@ -212,6 +216,9 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
MF.setAlignment(YamlMF.Alignment);
MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
MF.setHasInlineAsm(YamlMF.HasInlineAsm);
+ if (initializeRegisterInfo(MF.getRegInfo(), YamlMF))
+ return true;
+
const auto &F = *MF.getFunction();
for (const auto &YamlMBB : YamlMF.BasicBlocks) {
const BasicBlock *BB = nullptr;
@@ -250,6 +257,18 @@ bool MIRParserImpl::initializeMachineBasicBlock(
return false;
}
+bool MIRParserImpl::initializeRegisterInfo(
+ MachineRegisterInfo &RegInfo, const yaml::MachineFunction &YamlMF) {
+ assert(RegInfo.isSSA());
+ if (!YamlMF.IsSSA)
+ RegInfo.leaveSSA();
+ assert(RegInfo.tracksLiveness());
+ if (!YamlMF.TracksRegLiveness)
+ RegInfo.invalidateLiveness();
+ RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);
+ return false;
+}
+
SMDiagnostic MIRParserImpl::diagFromMIStringDiag(const SMDiagnostic &Error,
SMRange SourceRange) {
assert(SourceRange.isValid() && "Invalid source range");
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 801f6c25ac5..5d13890e1ab 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -15,6 +15,7 @@
#include "MIRPrinter.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Module.h"
@@ -38,6 +39,7 @@ public:
void print(const MachineFunction &MF);
+ void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo);
void convert(yaml::MachineBasicBlock &YamlMBB, const MachineBasicBlock &MBB);
};
@@ -78,6 +80,7 @@ void MIRPrinter::print(const MachineFunction &MF) {
YamlMF.Alignment = MF.getAlignment();
YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
YamlMF.HasInlineAsm = MF.hasInlineAsm();
+ convert(YamlMF, MF.getRegInfo());
for (const auto &MBB : MF) {
yaml::MachineBasicBlock YamlMBB;
convert(YamlMBB, MBB);
@@ -87,6 +90,13 @@ void MIRPrinter::print(const MachineFunction &MF) {
Out << YamlMF;
}
+void MIRPrinter::convert(yaml::MachineFunction &MF,
+ const MachineRegisterInfo &RegInfo) {
+ MF.IsSSA = RegInfo.isSSA();
+ MF.TracksRegLiveness = RegInfo.tracksLiveness();
+ MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
+}
+
void MIRPrinter::convert(yaml::MachineBasicBlock &YamlMBB,
const MachineBasicBlock &MBB) {
// TODO: Serialize unnamed BB references.
diff --git a/llvm/test/CodeGen/MIR/machine-function.mir b/llvm/test/CodeGen/MIR/machine-function.mir
index a3c1d1d7392..8f053adc22b 100644
--- a/llvm/test/CodeGen/MIR/machine-function.mir
+++ b/llvm/test/CodeGen/MIR/machine-function.mir
@@ -25,7 +25,7 @@
# CHECK-NEXT: alignment:
# CHECK-NEXT: exposesReturnsTwice: false
# CHECK-NEXT: hasInlineAsm: false
-# CHECK-NEXT: ...
+# CHECK: ...
name: foo
...
---
@@ -33,7 +33,7 @@ name: foo
# CHECK-NEXT: alignment:
# CHECK-NEXT: exposesReturnsTwice: false
# CHECK-NEXT: hasInlineAsm: false
-# CHECK-NEXT: ...
+# CHECK: ...
name: bar
...
---
@@ -41,7 +41,7 @@ name: bar
# CHECK-NEXT: alignment: 8
# CHECK-NEXT: exposesReturnsTwice: false
# CHECK-NEXT: hasInlineAsm: false
-# CHECK-NEXT: ...
+# CHECK: ...
name: func
alignment: 8
...
@@ -50,7 +50,7 @@ alignment: 8
# CHECK-NEXT: alignment: 16
# CHECK-NEXT: exposesReturnsTwice: true
# CHECK-NEXT: hasInlineAsm: true
-# CHECK-NEXT: ...
+# CHECK: ...
name: func2
alignment: 16
exposesReturnsTwice: true
diff --git a/llvm/test/CodeGen/MIR/register-info.mir b/llvm/test/CodeGen/MIR/register-info.mir
new file mode 100644
index 00000000000..c01997b4685
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/register-info.mir
@@ -0,0 +1,36 @@
+# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses machine register info properties
+# correctly.
+
+--- |
+
+ define i32 @foo() {
+ entry:
+ ret i32 0
+ }
+
+ define i32 @bar() {
+ start:
+ ret i32 0
+ }
+
+...
+---
+# CHECK: name: foo
+# CHECK: isSSA: false
+# CHECK-NEXT: tracksRegLiveness: false
+# CHECK-NEXT: tracksSubRegLiveness: false
+# CHECK: ...
+name: foo
+...
+---
+# CHECK: name: bar
+# CHECK: isSSA: false
+# CHECK-NEXT: tracksRegLiveness: true
+# CHECK-NEXT: tracksSubRegLiveness: true
+# CHECK: ...
+name: bar
+isSSA: false
+tracksRegLiveness: true
+tracksSubRegLiveness: true
+...
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