diff options
| -rw-r--r-- | llvm/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/sse4a.ll | 75 |
2 files changed, 65 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll index 77fa0a081df..efe133dd335 100644 --- a/llvm/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=X32 -; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=X64 +; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X64 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse4a-builtins.c diff --git a/llvm/test/CodeGen/X86/sse4a.ll b/llvm/test/CodeGen/X86/sse4a.ll index f8fa125f98e..4a2e09c5d07 100644 --- a/llvm/test/CodeGen/X86/sse4a.ll +++ b/llvm/test/CodeGen/X86/sse4a.ll @@ -1,9 +1,20 @@ -; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4a | FileCheck %s -; RUN: llc < %s -mtriple=x86_64-unknown-linux -mattr=sse4a | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X64 define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp { -; CHECK-LABEL: test1: -; CHECK: movntss +; X32-LABEL: test1: +; X32: # BB#0: +; X32-NEXT: movl {{[0-9]+}}(%esp), %eax +; X32-NEXT: movntss %xmm0, (%eax) +; X32-NEXT: retl +; +; X64-LABEL: test1: +; X64: # BB#0: +; X64-NEXT: movntss %xmm0, (%rdi) +; X64-NEXT: retq tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a) nounwind ret void } @@ -11,8 +22,16 @@ define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp { declare void @llvm.x86.sse4a.movnt.ss(i8*, <4 x float>) define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp { -; CHECK-LABEL: test2: -; CHECK: movntsd +; X32-LABEL: test2: +; X32: # BB#0: +; X32-NEXT: movl {{[0-9]+}}(%esp), %eax +; X32-NEXT: movntsd %xmm0, (%eax) +; X32-NEXT: retl +; +; X64-LABEL: test2: +; X64: # BB#0: +; X64-NEXT: movntsd %xmm0, (%rdi) +; X64-NEXT: retq tail call void @llvm.x86.sse4a.movnt.sd(i8* %p, <2 x double> %a) nounwind ret void } @@ -20,8 +39,15 @@ define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp { declare void @llvm.x86.sse4a.movnt.sd(i8*, <2 x double>) define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp { -; CHECK-LABEL: test3: -; CHECK: extrq +; X32-LABEL: test3: +; X32: # BB#0: +; X32-NEXT: extrq $2, $3, %xmm0 +; X32-NEXT: retl +; +; X64-LABEL: test3: +; X64: # BB#0: +; X64-NEXT: extrq $2, $3, %xmm0 +; X64-NEXT: retq %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2) ret <2 x i64> %1 } @@ -29,8 +55,15 @@ define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp { declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp { -; CHECK-LABEL: test4: -; CHECK: extrq +; X32-LABEL: test4: +; X32: # BB#0: +; X32-NEXT: extrq %xmm1, %xmm0 +; X32-NEXT: retl +; +; X64-LABEL: test4: +; X64: # BB#0: +; X64-NEXT: extrq %xmm1, %xmm0 +; X64-NEXT: retq %1 = bitcast <2 x i64> %y to <16 x i8> %2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind ret <2 x i64> %2 @@ -39,8 +72,15 @@ define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp { declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp { -; CHECK-LABEL: test5: -; CHECK: insertq +; X32-LABEL: test5: +; X32: # BB#0: +; X32-NEXT: insertq $6, $5, %xmm1, %xmm0 +; X32-NEXT: retl +; +; X64-LABEL: test5: +; X64: # BB#0: +; X64-NEXT: insertq $6, $5, %xmm1, %xmm0 +; X64-NEXT: retq %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6) ret <2 x i64> %1 } @@ -48,8 +88,15 @@ define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp { declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind define <2 x i64> @test6(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp { -; CHECK-LABEL: test6: -; CHECK: insertq +; X32-LABEL: test6: +; X32: # BB#0: +; X32-NEXT: insertq %xmm1, %xmm0 +; X32-NEXT: retl +; +; X64-LABEL: test6: +; X64: # BB#0: +; X64-NEXT: insertq %xmm1, %xmm0 +; X64-NEXT: retq %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind ret <2 x i64> %1 } |
