diff options
| -rw-r--r-- | llvm/test/Transforms/InstCombine/select-of-bittest.ll | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/select-of-bittest.ll b/llvm/test/Transforms/InstCombine/select-of-bittest.ll index 2b74cd07d81..5232a569e99 100644 --- a/llvm/test/Transforms/InstCombine/select-of-bittest.ll +++ b/llvm/test/Transforms/InstCombine/select-of-bittest.ll @@ -174,6 +174,24 @@ define i32 @f_var0(i32 %arg, i32 %arg1) { ret i32 %tmp5 } +; Should be exactly as the previous one +define i32 @f_var0_commutative_and(i32 %arg, i32 %arg1) { +; CHECK-LABEL: @f_var0_commutative_and( +; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG1:%.*]], [[ARG:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[ARG]], 1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 1 +; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP2]], i32 [[TMP4]], i32 1 +; CHECK-NEXT: ret i32 [[TMP5]] +; + %tmp = and i32 %arg1, %arg ; in different order + %tmp2 = icmp eq i32 %tmp, 0 + %tmp3 = lshr i32 %arg, 1 + %tmp4 = and i32 %tmp3, 1 + %tmp5 = select i1 %tmp2, i32 %tmp4, i32 1 + ret i32 %tmp5 +} + define <2 x i32> @f_var0_splatvec(<2 x i32> %arg, <2 x i32> %arg1) { ; CHECK-LABEL: @f_var0_splatvec( ; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[ARG1:%.*]], <i32 2, i32 2> @@ -238,6 +256,22 @@ define i32 @f_var1(i32 %arg, i32 %arg1) { ret i32 %tmp4 } +; Should be exactly as the previous one +define i32 @f_var1_commutative_and(i32 %arg, i32 %arg1) { +; CHECK-LABEL: @f_var1_commutative_and( +; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG1:%.*]], [[ARG:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[ARG]], 1 +; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 1 +; CHECK-NEXT: ret i32 [[TMP4]] +; + %tmp = and i32 %arg1, %arg ; in different order + %tmp2 = icmp eq i32 %tmp, 0 + %tmp3 = and i32 %arg, 1 + %tmp4 = select i1 %tmp2, i32 %tmp3, i32 1 + ret i32 %tmp4 +} + define <2 x i32> @f_var1_vec(<2 x i32> %arg, <2 x i32> %arg1) { ; CHECK-LABEL: @f_var1_vec( ; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[ARG1:%.*]], <i32 1, i32 1> @@ -361,6 +395,24 @@ define i32 @f_var3(i32 %arg, i32 %arg1, i32 %arg2) { ret i32 %tmp6 } +; Should be exactly as the previous one +define i32 @f_var3_commutative_and(i32 %arg, i32 %arg1, i32 %arg2) { +; CHECK-LABEL: @f_var3_commutative_and( +; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG1:%.*]], [[ARG:%.*]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP]], 0 +; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[ARG]], [[ARG2:%.*]] +; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 1 +; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP5]], i32 1 +; CHECK-NEXT: ret i32 [[TMP6]] +; + %tmp = and i32 %arg1, %arg ; in different order + %tmp3 = icmp eq i32 %tmp, 0 + %tmp4 = lshr i32 %arg, %arg2 + %tmp5 = and i32 %tmp4, 1 + %tmp6 = select i1 %tmp3, i32 %tmp5, i32 1 + ret i32 %tmp6 +} + define <2 x i32> @f_var3_splatvec(<2 x i32> %arg, <2 x i32> %arg1, <2 x i32> %arg2) { ; CHECK-LABEL: @f_var3_splatvec( ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> <i32 1, i32 1>, [[ARG2:%.*]] |
