diff options
| -rw-r--r-- | llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/MC/AsmParser/directive_seh.s | 46 |
2 files changed, 49 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index 54877adf800..25be79ec2b1 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -3749,11 +3749,10 @@ bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID, SMLoc startLoc = getLexer().getLoc(); const MCRegisterInfo *MRI = getContext().getRegisterInfo(); - // A percent indicates a symbolic register name. Parse it as usual and check - // the register class. - if (getLexer().is(AsmToken::Percent)) { + // Try parsing the argument as a register first. + if (getLexer().getTok().isNot(AsmToken::Integer)) { SMLoc endLoc; - if (getParser().getTargetParser().ParseRegister(RegNo, startLoc, endLoc)) + if (ParseRegister(RegNo, startLoc, endLoc)) return true; if (!X86MCRegisterClasses[RegClassID].contains(RegNo)) { diff --git a/llvm/test/MC/AsmParser/directive_seh.s b/llvm/test/MC/AsmParser/directive_seh.s index 139195dcb49..f4cd29fb5e9 100644 --- a/llvm/test/MC/AsmParser/directive_seh.s +++ b/llvm/test/MC/AsmParser/directive_seh.s @@ -1,5 +1,9 @@ # RUN: llvm-mc -triple x86_64-pc-win32 %s | FileCheck %s +# Round trip via intel syntax printing and back. +# RUN: llvm-mc -triple x86_64-pc-win32 %s -output-asm-variant=1 | \ +# RUN: llvm-mc -triple x86_64-pc-win32 -x86-asm-syntax=intel | FileCheck %s + .text .globl func .def func; .scl 2; .type 32; .endef @@ -51,3 +55,45 @@ func: ret .seh_endproc # CHECK: .seh_endproc + +# Re-run more or less the same test, but with intel syntax. Previously LLVM +# required percent prefixing in the .seh_* directives that take registers. + + .intel_syntax noprefix + .text + .globl func_intel + .def func_intel; .scl 2; .type 32; .endef + .seh_proc func_intel +# CHECK: .seh_proc func_intel +func_intel: + sub RSP, 24 + .seh_stackalloc 24 +# CHECK: .seh_stackalloc 24 + mov [16+RSP], RSI + .seh_savereg rsi, 16 +# CHECK: .seh_savereg %rsi, 16 + .seh_savereg 6, 16 +# CHECK: .seh_savereg %rsi, 16 + movups [RSP], XMM8 + .seh_savexmm XMM8, 0 +# CHECK: .seh_savexmm %xmm8, 0 + .seh_savexmm 8, 0 +# CHECK: .seh_savexmm %xmm8, 0 + push rbx + .seh_pushreg rbx +# CHECK: .seh_pushreg %rbx + .seh_pushreg 3 +# CHECK: .seh_pushreg %rbx + mov rbx, rsp + .seh_setframe rbx, 0 +# CHECK: .seh_setframe %rbx, 0 + .seh_endprologue +# CHECK: .seh_endprologue + .seh_handler __C_specific_handler, @except +# CHECK: .seh_handler __C_specific_handler, @except + .seh_handlerdata +# CHECK-NOT: .section{{.*}}.xdata +# CHECK: .seh_handlerdata + .long 0 + .text + .seh_endproc |
