diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index baa3b8bdc13..2760e16bd0f 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -195,7 +195,6 @@ namespace { unsigned DstSR, const MachineOperand &PredOp, bool PredSense, bool ReadUndef, bool ImpUse); bool split(MachineInstr &MI, std::set<unsigned> &UpdRegs); - bool splitInBlock(MachineBasicBlock &B, std::set<unsigned> &UpdRegs); bool isPredicable(MachineInstr *MI); MachineInstr *getReachingDefForPred(RegisterRef RD, @@ -651,22 +650,6 @@ bool HexagonExpandCondsets::split(MachineInstr &MI, return true; } - -/// Split all MUX instructions in the given block into pairs of conditional -/// transfers. -bool HexagonExpandCondsets::splitInBlock(MachineBasicBlock &B, - std::set<unsigned> &UpdRegs) { - bool Changed = false; - MachineBasicBlock::iterator I, E, NextI; - for (I = B.begin(), E = B.end(); I != E; I = NextI) { - NextI = std::next(I); - if (isCondset(*I)) - Changed |= split(*I, UpdRegs); - } - return Changed; -} - - bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) { if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) return false; |
