diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrArithmetic.td | 5 | ||||
| -rw-r--r-- | llvm/utils/TableGen/X86RecognizableInstr.cpp | 4 |
2 files changed, 4 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index fe00b8c787f..899d9a1cb63 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -497,7 +497,8 @@ def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1), Requires<[In64BitMode]>; } // isConvertibleToThreeAddress = 1, CodeSize = 2 -let isCodeGenOnly = 1, CodeSize = 2 in { +let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, + CodeSize = 2 in { def INC32_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1), "inc{w}\t$dst", [], IIC_UNARY_REG>, OpSize, Requires<[Not64BitMode]>; @@ -510,7 +511,7 @@ def DEC32_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1), def DEC32_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1), "dec{l}\t$dst", [], IIC_UNARY_REG>, Requires<[Not64BitMode]>; -} // isCodeGenOnly = 1, CodeSize = 2 +} // isCodeGenOnly = 1, ForceDisassemble = 1, HasSideEffects = 0, CodeSize = 2 } // Constraints = "$src1 = $dst", SchedRW diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index 2fac3519d2b..fffca0fc962 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -483,9 +483,7 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions"); - if (Form == X86Local::Pseudo || - (IsCodeGenOnly && !ForceDisassemble && - Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos)) + if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) return FILTER_STRONG; |
