diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/lower-vec-shuffle-bug.ll | 41 |
2 files changed, 44 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0533afc59f6..167685ac2a8 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -9021,12 +9021,12 @@ static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1, VT.getVectorNumElements() / 2); // Check for patterns which can be matched with a single insert of a 128-bit // subvector. - if (isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1}) || - isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) { + bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1}); + if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) { SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1, DAG.getIntPtrConstant(0)); SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, - Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0)); + OnlyUsesV1 ? V1 : V2, DAG.getIntPtrConstant(0)); return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV); } if (isShuffleEquivalent(V1, V2, Mask, {0, 1, 6, 7})) { diff --git a/llvm/test/CodeGen/X86/lower-vec-shuffle-bug.ll b/llvm/test/CodeGen/X86/lower-vec-shuffle-bug.ll new file mode 100644 index 00000000000..5918e8045f6 --- /dev/null +++ b/llvm/test/CodeGen/X86/lower-vec-shuffle-bug.ll @@ -0,0 +1,41 @@ +; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s + +define <4 x double> @test1(<4 x double> %A, <4 x double> %B) { +; CHECK-LABEL: test1: +; CHECK: # BB#0: +; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; CHECK-NEXT: retq +entry: + %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 undef, i32 1, i32 undef, i32 5> + ret <4 x double> %0 +} + +define <4 x double> @test2(<4 x double> %A, <4 x double> %B) { +; CHECK-LABEL: test2: +; CHECK: # BB#0: +; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; CHECK-NEXT: retq +entry: + %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 undef, i32 1, i32 undef, i32 1> + ret <4 x double> %0 +} + +define <4 x double> @test3(<4 x double> %A, <4 x double> %B) { +; CHECK-LABEL: test3: +; CHECK: # BB#0: +; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; CHECK-NEXT: retq +entry: + %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 0, i32 1, i32 undef, i32 5> + ret <4 x double> %0 +} + +define <4 x double> @test4(<4 x double> %A, <4 x double> %B) { +; CHECK-LABEL: test4: +; CHECK: # BB#0: +; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; CHECK-NEXT: retq +entry: + %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 0, i32 1, i32 undef, i32 1> + ret <4 x double> %0 +} |
