summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp8
-rw-r--r--llvm/test/CodeGen/PowerPC/testComparesigeui.ll6
-rw-r--r--llvm/test/CodeGen/PowerPC/testComparesllgeui.ll6
3 files changed, 10 insertions, 10 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 3fe9fe73499..af2ea695089 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -12228,8 +12228,12 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
EVT VT = N->getOperand(1).getValueType();
if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() &&
isa<ConstantSDNode>(N->getOperand(1)) && VT == MVT::i32) {
- SDValue Const64 = DAG.getConstant(N->getConstantOperandVal(1), dl,
- MVT::i64);
+ // Need to sign-extended to 64-bits to handle negative values.
+ EVT MemVT = cast<StoreSDNode>(N)->getMemoryVT();
+ uint64_t Val64 = SignExtend64(N->getConstantOperandVal(1),
+ MemVT.getSizeInBits());
+ SDValue Const64 = DAG.getConstant(Val64, dl, MVT::i64);
+
// DAG.getTruncStore() can't be used here because it doesn't accept
// the general (base + offset) addressing mode.
// So we use UpdateNodeOperands and setTruncatingStore instead.
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
index a77cea72cfa..ac55500432f 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
@@ -105,10 +105,8 @@ entry:
store i32 %conv1, i32* @glob
ret void
; CHECK-LABEL: @test_igeui_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], 0
-; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535
-; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535
-; CHECK: stw [[REG3]]
+; CHECK: li [[REG1:r[0-9]+]], -1
+; CHECK: stw [[REG1]]
; CHECK: blr
}
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
index 856d3a0f3cc..9e971b140de 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
@@ -105,10 +105,8 @@ entry:
store i32 %sub, i32* @glob
ret void
; CHECK-LABEL: @test_llgeui_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], 0
-; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535
-; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535
-; CHECK: stw [[REG3]]
+; CHECK: li [[REG1:r[0-9]+]], -1
+; CHECK: stw [[REG1]]
; CHECK: blr
}
OpenPOWER on IntegriCloud