diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedExynosM1.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td index 62a465048ee..7f1c2d4c764 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td +++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td @@ -440,14 +440,14 @@ def : InstRW<[M1WriteCOPY], (instrs COPY)>; // Miscellaneous instructions. // Load instructions. -def : InstRW<[M1WriteLC, - ReadAdrBase], (instregex "^LDR(BB|HH|SBW|SBX|SHW|SWX|SW|W|X)roW")>; -def : InstRW<[M1WriteL5, - ReadAdrBase], (instregex "^LDR(BB|HH|SBW|SBX|SHW|SWX|SW|W|X)roX")>; def : InstRW<[M1WriteLB, WriteLDHi, WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; def : InstRW<[M1WriteLC, + ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; +def : InstRW<[M1WriteL5, + ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; +def : InstRW<[M1WriteLC, ReadAdrBase], (instrs PRFMroW)>; def : InstRW<[M1WriteL5, ReadAdrBase], (instrs PRFMroX)>; |
