diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp | 18 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/swp-stages4.ll | 1 |
2 files changed, 5 insertions, 14 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp index ddf9c4cb185..a9e0c8f3918 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -153,9 +153,10 @@ bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { TotalPackets++; return false; } - // If this SU does not fit in the packet + // If this SU does not fit in the packet or the packet is now full // start a new one. - if (!isResourceAvailable(SU, IsTop)) { + if (!isResourceAvailable(SU, IsTop) || + Packet.size() >= SchedModel->getIssueWidth()) { ResourcesModel->clearResources(); Packet.clear(); TotalPackets++; @@ -189,15 +190,6 @@ bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { } #endif - // If packet is now full, reset the state so in the next cycle - // we start fresh. - if (Packet.size() >= SchedModel->getIssueWidth()) { - ResourcesModel->clearResources(); - Packet.clear(); - TotalPackets++; - startNewCycle = true; - } - return startNewCycle; } @@ -1100,10 +1092,10 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) { /// does. void ConvergingVLIWScheduler::schedNode(SUnit *SU, bool IsTopNode) { if (IsTopNode) { - SU->TopReadyCycle = Top.CurrCycle; Top.bumpNode(SU); + SU->TopReadyCycle = Top.CurrCycle; } else { - SU->BotReadyCycle = Bot.CurrCycle; Bot.bumpNode(SU); + SU->BotReadyCycle = Bot.CurrCycle; } } diff --git a/llvm/test/CodeGen/Hexagon/swp-stages4.ll b/llvm/test/CodeGen/Hexagon/swp-stages4.ll index 9a0bb9e8f5a..2d88094cf74 100644 --- a/llvm/test/CodeGen/Hexagon/swp-stages4.ll +++ b/llvm/test/CodeGen/Hexagon/swp-stages4.ll @@ -12,7 +12,6 @@ ; CHECK: .LBB0_[[LOOP]]: ; CHECK: = add(r{{[0-9]+}},r[[REG0]]) ; CHECK: = and -; CHECK: = and ; CHECK: r[[REG0]] = and ; CHECK: endloop |
