diff options
| -rw-r--r-- | llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h | 13 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 24 |
3 files changed, 32 insertions, 10 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h index 60905c7ec22..02868b22098 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h @@ -407,6 +407,10 @@ protected: mutable DenseMap<unsigned, std::unique_ptr<const InstructionMapping>> MapOfInstructionMappings; + /// Getting the minimal register class of a physreg is expensive. + /// Cache this information as we get it. + mutable DenseMap<unsigned, const TargetRegisterClass *> PhysRegMinimalRCs; + /// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks /// RegisterBank instances. RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks); @@ -427,6 +431,11 @@ protected: return *RegBanks[ID]; } + /// Get the MinimalPhysRegClass for Reg. + /// \pre Reg is a physical register. + const TargetRegisterClass & + getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const; + /// Try to get the mapping of \p MI. /// See getInstrMapping for more details on what a mapping represents. /// @@ -699,8 +708,8 @@ public: /// virtual register. /// /// \pre \p Reg != 0 (NoRegister). - static unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, - const TargetRegisterInfo &TRI); + unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, + const TargetRegisterInfo &TRI) const; /// Check that information hold by this instance make sense for the /// given \p TRI. diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp index f2eb217c0b8..fac26a16412 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp @@ -221,9 +221,8 @@ uint64_t RegBankSelect::getRepairCost( // into a new virtual register. // We would also need to propagate this information in the // repairing placement. - unsigned Cost = - RBI->copyCost(*DesiredRegBrank, *CurRegBank, - RegisterBankInfo::getSizeInBits(MO.getReg(), *MRI, *TRI)); + unsigned Cost = RBI->copyCost(*DesiredRegBrank, *CurRegBank, + RBI->getSizeInBits(MO.getReg(), *MRI, *TRI)); // TODO: use a dedicated constant for ImpossibleCost. if (Cost != std::numeric_limits<unsigned>::max()) return Cost; diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp index 3d7132717cc..cad1bd68adf 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -84,7 +84,7 @@ const RegisterBank * RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const { if (TargetRegisterInfo::isPhysicalRegister(Reg)) - return &getRegBankFromRegClass(*TRI.getMinimalPhysRegClass(Reg)); + return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI)); assert(Reg && "NoRegister does not have a register bank"); const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg); @@ -95,6 +95,19 @@ RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, return nullptr; } +const TargetRegisterClass & +RegisterBankInfo::getMinimalPhysRegClass(unsigned Reg, + const TargetRegisterInfo &TRI) const { + assert(TargetRegisterInfo::isPhysicalRegister(Reg) && + "Reg must be a physreg"); + const auto &RegRCIt = PhysRegMinimalRCs.find(Reg); + if (RegRCIt != PhysRegMinimalRCs.end()) + return *RegRCIt->second; + const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg); + PhysRegMinimalRCs[Reg] = PhysRC; + return *PhysRC; +} + const RegisterBank *RegisterBankInfo::getRegBankFromConstraints( const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const { @@ -441,13 +454,13 @@ void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) { unsigned RegisterBankInfo::getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, - const TargetRegisterInfo &TRI) { + const TargetRegisterInfo &TRI) const { const TargetRegisterClass *RC = nullptr; if (TargetRegisterInfo::isPhysicalRegister(Reg)) { // The size is not directly available for physical registers. // Instead, we need to access a register class that contains Reg and // get the size of that register class. - RC = TRI.getMinimalPhysRegClass(Reg); + RC = &getMinimalPhysRegClass(Reg, TRI); } else { LLT Ty = MRI.getType(Reg); unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0; @@ -546,7 +559,8 @@ bool RegisterBankInfo::InstructionMapping::verify( assert(MI.getParent() && MI.getMF() && "MI must be connected to a MachineFunction"); const MachineFunction &MF = *MI.getMF(); - (void)MF; + const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo(); + (void)RBI; for (unsigned Idx = 0; Idx < NumOperands; ++Idx) { const MachineOperand &MO = MI.getOperand(Idx); @@ -564,7 +578,7 @@ bool RegisterBankInfo::InstructionMapping::verify( (void)MOMapping; // Register size in bits. // This size must match what the mapping expects. - assert(MOMapping.verify(getSizeInBits( + assert(MOMapping.verify(RBI->getSizeInBits( Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) && "Value mapping is invalid"); } |
