diff options
| -rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll | 18 |
2 files changed, 25 insertions, 0 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index 125c74a89a1..0a622424368 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -40,6 +40,13 @@ static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, // This instruction is producing bits that are not demanded. Shrink the RHS. Demanded &= OpC->getValue(); + if (I->getOpcode() == Instruction::Add) { + // However, if the instruction is an add then the constant may be negated + // when the opcode is changed to sub. Check if the transformation is really + // shrinking the constant. + if (Demanded.abs().getActiveBits() > OpC->getValue().abs().getActiveBits()) + return false; + } I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded)); return true; } diff --git a/llvm/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll b/llvm/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll new file mode 100644 index 00000000000..d62a8864d71 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll @@ -0,0 +1,18 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +; When shrinking demanded constant operand of an add instruction, keep in +; mind the opcode can be changed to sub and the constant negated. Make sure +; the shrinking the constant would actually reduce the width. +; rdar://11793464 + +define i64 @t(i64 %key, i64* %val) nounwind { +entry: +; CHECK: @t +; CHECK-NOT: add i64 %0, 2305843009213693951 +; CHECK: add i64 %0, -1 + %shr = lshr i64 %key, 3 + %0 = load i64* %val, align 8 + %sub = sub i64 %0, 1 + %and = and i64 %sub, %shr + ret i64 %and +} |
