diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 45 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.h | 20 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 21 |
3 files changed, 8 insertions, 78 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index f3df5f557ca..88456e07d4f 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -4809,51 +4809,6 @@ static bool canWidenShuffleElements(ArrayRef<int> Mask, return true; } -/// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector -/// extract that is suitable for instruction that extract 128 or 256 bit vectors -static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) { - assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width"); - if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) - return false; - - // The index should be aligned on a vecWidth-bit boundary. - uint64_t Index = N->getConstantOperandVal(1); - MVT VT = N->getSimpleValueType(0); - unsigned ElSize = VT.getScalarSizeInBits(); - return (Index * ElSize) % vecWidth == 0; -} - -/// Return true if the specified INSERT_SUBVECTOR -/// operand specifies a subvector insert that is suitable for input to -/// insertion of 128 or 256-bit subvectors -static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) { - assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width"); - if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) - return false; - - // The index should be aligned on a vecWidth-bit boundary. - uint64_t Index = N->getConstantOperandVal(2); - MVT VT = N->getSimpleValueType(0); - unsigned ElSize = VT.getScalarSizeInBits(); - return (Index * ElSize) % vecWidth == 0; -} - -bool X86::isVINSERT128Index(SDNode *N) { - return isVINSERTIndex(N, 128); -} - -bool X86::isVINSERT256Index(SDNode *N) { - return isVINSERTIndex(N, 256); -} - -bool X86::isVEXTRACT128Index(SDNode *N) { - return isVEXTRACTIndex(N, 128); -} - -bool X86::isVEXTRACT256Index(SDNode *N) { - return isVEXTRACTIndex(N, 256); -} - static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) { assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width"); assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) && diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 8f60a33e8d3..849fe962e2b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -624,26 +624,6 @@ namespace llvm { /// Define some predicates that are used for node matching. namespace X86 { - /// Return true if the specified - /// EXTRACT_SUBVECTOR operand specifies a vector extract that is - /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions. - bool isVEXTRACT128Index(SDNode *N); - - /// Return true if the specified - /// INSERT_SUBVECTOR operand specifies a subvector insert that is - /// suitable for input to VINSERTF128, VINSERTI128 instructions. - bool isVINSERT128Index(SDNode *N); - - /// Return true if the specified - /// EXTRACT_SUBVECTOR operand specifies a vector extract that is - /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions. - bool isVEXTRACT256Index(SDNode *N); - - /// Return true if the specified - /// INSERT_SUBVECTOR operand specifies a subvector insert that is - /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions. - bool isVINSERT256Index(SDNode *N); - /// Return the appropriate /// immediate to extract the specified EXTRACT_SUBVECTOR index /// with VEXTRACTF128, VEXTRACTI128 instructions. diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td index b5f3033b3cd..3ccd07342b9 100644 --- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -907,30 +907,25 @@ def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{ def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index), (extract_subvector node:$bigvec, - node:$index), [{ - return X86::isVEXTRACT128Index(N); -}], EXTRACT_get_vextract128_imm>; + node:$index), [{}], + EXTRACT_get_vextract128_imm>; def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec, node:$index), (insert_subvector node:$bigvec, node:$smallvec, - node:$index), [{ - return X86::isVINSERT128Index(N); -}], INSERT_get_vinsert128_imm>; - + node:$index), [{}], + INSERT_get_vinsert128_imm>; def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index), (extract_subvector node:$bigvec, - node:$index), [{ - return X86::isVEXTRACT256Index(N); -}], EXTRACT_get_vextract256_imm>; + node:$index), [{}], + EXTRACT_get_vextract256_imm>; def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec, node:$index), (insert_subvector node:$bigvec, node:$smallvec, - node:$index), [{ - return X86::isVINSERT256Index(N); -}], INSERT_get_vinsert256_imm>; + node:$index), [{}], + INSERT_get_vinsert256_imm>; def X86mload : PatFrag<(ops node:$src1, node:$src2, node:$src3), (masked_load node:$src1, node:$src2, node:$src3), [{ |
