diff options
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 40 |
1 files changed, 25 insertions, 15 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 6eb01b270a4..942a3a8a589 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1356,9 +1356,11 @@ public: template <unsigned Bits, unsigned ShiftLeftAmount> bool isScaledSImm() const { - if (isConstantImm() && isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm())) + if (isConstantImm() && + isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm())) return true; - // Operand can also be a symbol or symbol plus offset in case of relocations. + // Operand can also be a symbol or symbol plus + // offset in case of relocations. if (Kind != k_Immediate) return false; MCValue Res; @@ -2064,7 +2066,8 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, // FIXME: Add support for forward-declared local symbols. // FIXME: Add expansion for when the LargeGOT option is enabled. if (JalSym->isInSection() || JalSym->isTemporary() || - (JalSym->isELF() && cast<MCSymbolELF>(JalSym)->getBinding() == ELF::STB_LOCAL)) { + (JalSym->isELF() && + cast<MCSymbolELF>(JalSym)->getBinding() == ELF::STB_LOCAL)) { if (isABI_O32()) { // If it's a local symbol and the O32 ABI is being used, we expand to: // lw $25, 0($gp) @@ -3554,11 +3557,10 @@ bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI, bool IsLoad, bool IsImmOpnd) { - if (IsLoad) { + if (IsLoad) expandLoadInst(Inst, IDLoc, Out, STI, IsImmOpnd); - return; - } - expandStoreInst(Inst, IDLoc, Out, STI, IsImmOpnd); + else + expandStoreInst(Inst, IDLoc, Out, STI, IsImmOpnd); } void MipsAsmParser::expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, @@ -3764,7 +3766,8 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, case Mips::BLTUL: AcceptsEquality = false; ReverseOrderSLT = false; - IsUnsigned = ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL)); + IsUnsigned = + ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL)); IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL)); ZeroSrcOpcode = Mips::BGTZ; ZeroTrgOpcode = Mips::BLTZ; @@ -3775,7 +3778,8 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, case Mips::BLEUL: AcceptsEquality = true; ReverseOrderSLT = true; - IsUnsigned = ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL)); + IsUnsigned = + ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL)); IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL)); ZeroSrcOpcode = Mips::BGEZ; ZeroTrgOpcode = Mips::BLEZ; @@ -3786,7 +3790,8 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, case Mips::BGEUL: AcceptsEquality = true; ReverseOrderSLT = false; - IsUnsigned = ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL)); + IsUnsigned = + ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL)); IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL)); ZeroSrcOpcode = Mips::BLEZ; ZeroTrgOpcode = Mips::BGEZ; @@ -3797,7 +3802,8 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, case Mips::BGTUL: AcceptsEquality = false; ReverseOrderSLT = true; - IsUnsigned = ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL)); + IsUnsigned = + ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL)); IsLikely = ((PseudoOpcode == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL)); ZeroSrcOpcode = Mips::BLTZ; ZeroTrgOpcode = Mips::BGTZ; @@ -4317,7 +4323,8 @@ bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, DstReg = ATReg; } - if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, Inst.getLoc(), Out, STI)) { + if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, + Inst.getLoc(), Out, STI)) { switch (FinalOpcode) { default: llvm_unreachable("unimplemented expansion"); @@ -4705,7 +4712,8 @@ bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, if (!ATReg) return true; - loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out, STI); + loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out, + STI); TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT, SrcReg, ATReg, IDLoc, STI); @@ -5335,7 +5343,8 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return Error(ErrorLoc, "invalid operand for instruction"); } case Match_NonZeroOperandForSync: - return Error(IDLoc, "s-type must be zero or unspecified for pre-MIPS32 ISAs"); + return Error(IDLoc, + "s-type must be zero or unspecified for pre-MIPS32 ISAs"); case Match_NonZeroOperandForMTCX: return Error(IDLoc, "selector must be zero for pre-MIPS32 ISAs"); case Match_MnemonicFail: @@ -7241,7 +7250,8 @@ bool MipsAsmParser::parseDirectiveSet() { return false; } else if (Tok.getString() == "micromips") { if (hasMips64r6()) { - Error(Tok.getLoc(), ".set micromips directive is not supported with MIPS64R6"); + Error(Tok.getLoc(), + ".set micromips directive is not supported with MIPS64R6"); return false; } return parseSetFeature(Mips::FeatureMicroMips); |
