diff options
| -rw-r--r-- | llvm/lib/CodeGen/MIRParser/MIParser.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp | 2 |
3 files changed, 5 insertions, 8 deletions
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index cac22af3295..00003b51787 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -1949,8 +1949,7 @@ bool MIParser::getHexUint(APInt &Result) { return true; StringRef V = S.substr(2); APInt A(V.size()*4, V, 16); - Result = APInt(A.getActiveBits(), - ArrayRef<uint64_t>(A.getRawData(), A.getNumWords())); + Result = A.zextOrTrunc(A.getActiveBits()); return false; } diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index c1cb5d9b523..c8a9dcbfe23 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -158,9 +158,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N, unsigned ResNo) { // and the low 64 bits here. if (DAG.getDataLayout().isBigEndian() && CN->getValueType(0).getSimpleVT() == llvm::MVT::ppcf128) { - uint64_t words[2] = { CN->getValueAPF().bitcastToAPInt().getRawData()[1], - CN->getValueAPF().bitcastToAPInt().getRawData()[0] }; - APInt Val(128, words); + APInt Val = CN->getValueAPF().bitcastToAPInt().rotl(64); return DAG.getConstant(Val, SDLoc(CN), TLI.getTypeToTransformTo(*DAG.getContext(), CN->getValueType(0))); @@ -1060,10 +1058,10 @@ void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt(); SDLoc dl(N); Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT), - APInt(64, C.getRawData()[1])), + C.extractBits(64, 64)), dl, NVT); Hi = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT), - APInt(64, C.getRawData()[0])), + C.extractBits(64, 0)), dl, NVT); } diff --git a/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp b/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp index 7189b5a52c4..39f43988b19 100644 --- a/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp @@ -124,7 +124,7 @@ void llvm::HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, // FP immediates are used only when setting GPRs, so they may be dealt // with like regular immediates from this point on. auto Expr = HexagonMCExpr::create( - MCConstantExpr::create(*Val.bitcastToAPInt().getRawData(), + MCConstantExpr::create(Val.bitcastToAPInt().getZExtValue(), AP.OutContext), AP.OutContext); HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend); |
