diff options
| -rw-r--r-- | llvm/include/llvm/CodeGen/MachineInstr.h | 1 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir | 4 |
5 files changed, 20 insertions, 3 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h index 989e6fc9223..c76bcdedf0e 100644 --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -190,6 +190,7 @@ public: void setType(LLT Ty, unsigned Idx = 0); LLT getType(int unsigned = 0) const; unsigned getNumTypes() const; + void removeTypes(); /// Return true if MI is in a bundle (but not the first MI in a bundle). /// diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index ac5ce811f3a..ca3799db1ed 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -716,6 +716,8 @@ void MachineInstr::setType(LLT Ty, unsigned Idx) {} LLT MachineInstr::getType(unsigned Idx) const { return LLT{}; } +void MachineInstr::removeTypes() {} + #else unsigned MachineInstr::getNumTypes() const { return Tys.size(); } @@ -728,6 +730,10 @@ void MachineInstr::setType(LLT Ty, unsigned Idx) { } LLT MachineInstr::getType(unsigned Idx) const { return Tys[Idx]; } + +void MachineInstr::removeTypes() { + Tys.clear(); +} #endif // LLVM_BUILD_GLOBAL_ISEL /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 23a89f865c1..8f8013adc98 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -879,6 +879,16 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { } } + // Check types. + const unsigned NumTypes = MI->getNumTypes(); + if (isPreISelGenericOpcode(MCID.getOpcode())) { + if (NumTypes == 0) + report("Generic instruction must have a type", MI); + } else { + if (NumTypes != 0) + report("Non-generic instruction cannot have a type", MI); + } + StringRef ErrorInfo; if (!TII->verifyInstruction(*MI, ErrorInfo)) report(ErrorInfo.data(), MI); diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 6899950c263..26b574af464 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -150,7 +150,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { I.setDesc(TII.get(NewOpc)); // FIXME: Should the type be always reset in setDesc? - I.setType(LLT()); + I.removeTypes(); // Now that we selected an opcode, we need to constrain the register // operands to use appropriate classes. diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir index 0d9cdbee0c8..67851e5c80d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=instruction-select -global-isel %s -o - | FileCheck %s +# RUN: llc -O0 -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s # REQUIRES: global-isel # Test the instruction selector. @@ -6,7 +6,7 @@ --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64-apple-ios" + target triple = "aarch64--" define void @add_s32_gpr() { ret void } define void @add_s64_gpr() { ret void } |
