diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/extractelement-shuffle.ll | 13 |
2 files changed, 15 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index aae4c59a8c7..9cc8061f183 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4874,7 +4874,8 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { MVT LVT = EVT; if (InVec.getOpcode() == ISD::BIT_CONVERT) { MVT BCVT = InVec.getOperand(0).getValueType(); - if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) + if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()) || + VT.getVectorNumElements() != BCVT.getVectorNumElements()) return SDValue(); InVec = InVec.getOperand(0); EVT = BCVT.getVectorElementType(); diff --git a/llvm/test/CodeGen/X86/extractelement-shuffle.ll b/llvm/test/CodeGen/X86/extractelement-shuffle.ll new file mode 100644 index 00000000000..b00c8e49e1c --- /dev/null +++ b/llvm/test/CodeGen/X86/extractelement-shuffle.ll @@ -0,0 +1,13 @@ +; RUN: llvm-as < %s | llc + +; Examples that exhibits a bug in DAGCombine. The case is triggered by the +; following program. The bug is DAGCombine assumes that the bit convert +; preserves the number of elements so the optimization code tries to read +; through the 3rd mask element, which doesn't exist. +define i32 @update(<2 x i64> %val1, <2 x i64> %val2) nounwind readnone { +entry: + %shuf = shufflevector <2 x i64> %val1, <2 x i64> %val2, <2 x i32> <i32 0, i32 3>; + %bit = bitcast <2 x i64> %shuf to <4 x i32>; + %res = extractelement <4 x i32> %bit, i32 3; + ret i32 %res; +}
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