diff options
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZInstrFormats.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZRegisterInfo.td | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/int-cmp-51.ll | 34 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/memchr-01.ll | 2 |
5 files changed, 41 insertions, 5 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td index 71eb9986499..01f4cdec05c 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -2381,6 +2381,7 @@ multiclass StringRRE<string mnemonic, bits<16> opcode, def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2), (ins GR64:$R1src, GR64:$R2src), mnemonic#"\t$R1, $R2", []> { + let Uses = [R0L]; let Constraints = "$R1 = $R1src, $R2 = $R2src"; let DisableEncoding = "$R1src, $R2src"; } diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td index 628c51a48ef..b9f2eb5514a 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -397,7 +397,7 @@ let mayLoad = 1, mayStore = 1 in defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; // String moves. -let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L] in +let mayLoad = 1, mayStore = 1, Defs = [CC] in defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; //===----------------------------------------------------------------------===// @@ -1185,7 +1185,7 @@ let mayLoad = 1, Defs = [CC] in defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>; // String comparison. -let mayLoad = 1, Defs = [CC], Uses = [R0L] in +let mayLoad = 1, Defs = [CC] in defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; // Test under mask. @@ -1459,7 +1459,7 @@ let usesCustomInserter = 1 in { } // Search a block of memory for a character. -let mayLoad = 1, Defs = [CC], Uses = [R0L] in +let mayLoad = 1, Defs = [CC] in defm SRST : StringRRE<"srst", 0xb25e, z_search_string>; // Other instructions for inline assembly diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td index 85aa0a62cc7..0d8b08b9cbd 100644 --- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td @@ -282,4 +282,5 @@ def v128any : TypedReg<untyped, VR128>; // The 2-bit condition code field of the PSW. Every register named in an // inline asm needs a class associated with it. def CC : SystemZReg<"cc">; -def CCRegs : RegisterClass<"SystemZ", [i32], 32, (add CC)>; +let isAllocatable = 0 in + def CCRegs : RegisterClass<"SystemZ", [i32], 32, (add CC)>; diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-51.ll b/llvm/test/CodeGen/SystemZ/int-cmp-51.ll new file mode 100644 index 00000000000..85a0e4b4d3a --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/int-cmp-51.ll @@ -0,0 +1,34 @@ +; Check that modelling of CC/CCRegs does not stop MachineCSE from +; removing a compare. MachineCSE will not extend a live range of an +; allocatable or reserved phys reg. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare void @bar(i8) + +; Check the low end of the CH range. +define void @f1(i32 %lhs) { +; CHECK-LABEL: BB#1: +; CHECK-NOT: cijlh %r0, 1, .LBB0_3 + +entry: + %and188 = and i32 %lhs, 255 + %cmp189 = icmp ult i32 %and188, 2 + br i1 %cmp189, label %if.then.191, label %if.else.201 + +if.then.191: + %cmp194 = icmp eq i32 %and188, 1 + br i1 %cmp194, label %if.then.196, label %if.else.198 + +if.then.196: + call void @bar(i8 1); + br label %if.else.201 + +if.else.198: + call void @bar(i8 0); + br label %if.else.201 + +if.else.201: + ret void +} + diff --git a/llvm/test/CodeGen/SystemZ/memchr-01.ll b/llvm/test/CodeGen/SystemZ/memchr-01.ll index c51690b9848..f7509c4f256 100644 --- a/llvm/test/CodeGen/SystemZ/memchr-01.ll +++ b/llvm/test/CodeGen/SystemZ/memchr-01.ll @@ -1,6 +1,6 @@ ; Test memchr using SRST, with a weird but usable prototype. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs | FileCheck %s declare i8 *@memchr(i8 *%src, i16 %char, i32 %len) |
