diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll | 11 |
2 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 1115d8c2362..8912ef44603 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -4435,6 +4435,9 @@ void AMDGPUTargetLowering::computeKnownBitsForTargetNode( unsigned TrailZ = LHSKnown.countMinTrailingZeros() + RHSKnown.countMinTrailingZeros(); Known.Zero.setLowBits(std::min(TrailZ, 32u)); + // Skip extra check if all bits are known zeros. + if (TrailZ >= 32) + break; // Truncate to 24 bits. LHSKnown = LHSKnown.trunc(24); diff --git a/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll b/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll index 125f76ae10e..6f3659cbd94 100644 --- a/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll +++ b/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll @@ -157,3 +157,14 @@ define i32 @num_sign_bits_mul_i32_10(i32 %x, i32 %y, i32 %z, i32 %w) { %mul2 = mul i32 %mul0, %mul1 ret i32 %mul2 } + +; GFX9-LABEL: known_bits_mul24: +; GFX9: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_setpc_b64 +define i32 @known_bits_mul24() { + %r0 = call i32 @llvm.amdgcn.mul.i24(i32 0, i32 -7) + %r1 = shl i32 %r0, 2 + ret i32 %r1 +} + +declare i32 @llvm.amdgcn.mul.i24(i32, i32) |
