diff options
5 files changed, 209 insertions, 1 deletions
diff --git a/polly/lib/CodeGen/BlockGenerators.cpp b/polly/lib/CodeGen/BlockGenerators.cpp index 1fe15e4fb28..9bff9d2a1b9 100644 --- a/polly/lib/CodeGen/BlockGenerators.cpp +++ b/polly/lib/CodeGen/BlockGenerators.cpp @@ -558,7 +558,8 @@ void BlockGenerator::generateScalarLoads( continue; #ifndef NDEBUG - auto StmtDom = Stmt.getDomain(); + auto StmtDom = + Stmt.getDomain().intersect_params(Stmt.getParent()->getContext()); auto AccDom = MA->getAccessRelation().domain(); assert(!StmtDom.is_subset(AccDom).is_false() && "Scalar must be loaded in all statement instances"); diff --git a/polly/lib/Exchange/JSONExporter.cpp b/polly/lib/Exchange/JSONExporter.cpp index 512c51558c6..943d1b2d983 100644 --- a/polly/lib/Exchange/JSONExporter.cpp +++ b/polly/lib/Exchange/JSONExporter.cpp @@ -512,6 +512,8 @@ importAccesses(Scop &S, Json::Value &JScop, const DataLayout &DL, isl_set_intersect_params(NewAccessDomain, S.getContext().release()); CurrentAccessDomain = isl_set_intersect_params(CurrentAccessDomain, S.getContext().release()); + CurrentAccessDomain = + isl_set_intersect(CurrentAccessDomain, Stmt.getDomain().release()); if (MA->isRead() && isl_set_is_subset(CurrentAccessDomain, NewAccessDomain) == diff --git a/polly/test/Isl/CodeGen/load_subset_with_context.ll b/polly/test/Isl/CodeGen/load_subset_with_context.ll new file mode 100644 index 00000000000..10fb0f00586 --- /dev/null +++ b/polly/test/Isl/CodeGen/load_subset_with_context.ll @@ -0,0 +1,57 @@ +; RUN: opt %loadPolly -polly-import-jscop -polly-import-jscop-postfix=transformed -polly-codegen -S < %s | FileCheck %s +; +; A load must provide a value for every statement instance. +; Statement instances not in the SCoP's context are irrelevant. +; +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + +@ATH = external dso_local unnamed_addr constant [88 x float], align 16 + +define void @load_subset_with_context() { +entry: + %ath = alloca [56 x float], align 16 + br label %for.body + +for.cond176.preheader: ; preds = %for.cond33.preheader + ret void + +for.body: ; preds = %for.cond33.preheader, %entry + %indvars.iv999 = phi i64 [ 0, %entry ], [ %indvars.iv.next1000, %for.cond33.preheader ] + %tmp5 = shl nsw i64 %indvars.iv999, 2 + br label %for.cond7.preheader + +for.cond33.preheader: ; preds = %for.inc.3 + %tmp175 = load float, float* undef, align 4 + %indvars.iv.next1000 = add nuw nsw i64 %indvars.iv999, 1 + %exitcond1002 = icmp eq i64 %indvars.iv.next1000, 17 + br i1 %exitcond1002, label %for.cond176.preheader, label %for.body + +for.cond7.preheader: ; preds = %for.inc.3, %for.body + %indvars.iv958 = phi i64 [ 0, %for.body ], [ %indvars.iv.next959, %for.inc.3 ] + %tmp20 = add nuw nsw i64 %indvars.iv958, %tmp5 + %arrayidx.2 = getelementptr inbounds [88 x float], [88 x float]* @ATH, i64 0, i64 0 + %tmp157 = load float, float* %arrayidx.2, align 4 + %tmp158 = add nuw nsw i64 %tmp20, 3 + %cmp12.3 = icmp ult i64 %tmp158, 88 + br i1 %cmp12.3, label %if.then.3, label %if.else.3 + +if.else.3: ; preds = %for.cond7.preheader + br label %for.inc.3 + +if.then.3: ; preds = %for.cond7.preheader + br label %for.inc.3 + +for.inc.3: ; preds = %if.then.3, %if.else.3 + %min.1.3 = phi float [ undef, %if.then.3 ], [ %tmp157, %if.else.3 ] + %arrayidx29 = getelementptr inbounds [56 x float], [56 x float]* %ath, i64 0, i64 %indvars.iv958 + store float %min.1.3, float* %arrayidx29, align 4 + %indvars.iv.next959 = add nuw nsw i64 %indvars.iv958, 1 + %exitcond961 = icmp eq i64 %indvars.iv.next959, 56 + br i1 %exitcond961, label %for.cond33.preheader, label %for.cond7.preheader +} + + +; CHECK: polly.stmt.if.else.3: +; CHECK-NEXT: %polly.access.cast.ath1 = bitcast [56 x float]* %ath to float* +; CHECK-NEXT: %polly.access.ath2 = getelementptr float, float* %polly.access.cast.ath1, i64 %polly.indvar +; CHECK-NEXT: %polly.access.ath2.reload = load float, float* %polly.access.ath2 diff --git a/polly/test/Isl/CodeGen/load_subset_with_context___%for.cond7.preheader---%for.cond33.preheader.jscop b/polly/test/Isl/CodeGen/load_subset_with_context___%for.cond7.preheader---%for.cond33.preheader.jscop new file mode 100644 index 00000000000..6b137dda057 --- /dev/null +++ b/polly/test/Isl/CodeGen/load_subset_with_context___%for.cond7.preheader---%for.cond33.preheader.jscop @@ -0,0 +1,74 @@ +{ + "arrays" : [ + { + "name" : "MemRef_ATH", + "sizes" : [ "*" ], + "type" : "float" + }, + { + "name" : "MemRef_ath", + "sizes" : [ "*" ], + "type" : "float" + } + ], + "context" : "[p_0] -> { : 0 <= p_0 <= 16 }", + "name" : "%for.cond7.preheader---%for.cond33.preheader", + "statements" : [ + { + "accesses" : [ + { + "kind" : "read", + "relation" : "[p_0] -> { Stmt_for_cond7_preheader[i0] -> MemRef_ATH[0] }" + }, + { + "kind" : "write", + "relation" : "[p_0] -> { Stmt_for_cond7_preheader[i0] -> MemRef_tmp157[] }" + } + ], + "domain" : "[p_0] -> { Stmt_for_cond7_preheader[i0] : 0 <= i0 <= 55 }", + "name" : "Stmt_for_cond7_preheader", + "schedule" : "[p_0] -> { Stmt_for_cond7_preheader[i0] -> [i0, 0] }" + }, + { + "accesses" : [ + { + "kind" : "write", + "relation" : "[p_0] -> { Stmt_if_then_3[i0] -> MemRef_min_1_3__phi[] }" + } + ], + "domain" : "[p_0] -> { Stmt_if_then_3[i0] : 0 <= i0 <= 84 - 4p_0 and i0 <= 55 }", + "name" : "Stmt_if_then_3", + "schedule" : "[p_0] -> { Stmt_if_then_3[i0] -> [i0, 2] }" + }, + { + "accesses" : [ + { + "kind" : "read", + "relation" : "[p_0] -> { Stmt_if_else_3[i0] -> MemRef_tmp157[] }" + }, + { + "kind" : "write", + "relation" : "[p_0] -> { Stmt_if_else_3[i0] -> MemRef_min_1_3__phi[] }" + } + ], + "domain" : "[p_0] -> { Stmt_if_else_3[i0] : 85 - 4p_0 <= i0 <= 55 }", + "name" : "Stmt_if_else_3", + "schedule" : "[p_0] -> { Stmt_if_else_3[i0] -> [i0, 1] }" + }, + { + "accesses" : [ + { + "kind" : "read", + "relation" : "[p_0] -> { Stmt_for_inc_3[i0] -> MemRef_min_1_3__phi[] }" + }, + { + "kind" : "write", + "relation" : "[p_0] -> { Stmt_for_inc_3[i0] -> MemRef_ath[i0] }" + } + ], + "domain" : "[p_0] -> { Stmt_for_inc_3[i0] : 0 <= i0 <= 55 }", + "name" : "Stmt_for_inc_3", + "schedule" : "[p_0] -> { Stmt_for_inc_3[i0] -> [i0, 3] }" + } + ] +} diff --git a/polly/test/Isl/CodeGen/load_subset_with_context___%for.cond7.preheader---%for.cond33.preheader.jscop.transformed b/polly/test/Isl/CodeGen/load_subset_with_context___%for.cond7.preheader---%for.cond33.preheader.jscop.transformed new file mode 100644 index 00000000000..2bfd409961b --- /dev/null +++ b/polly/test/Isl/CodeGen/load_subset_with_context___%for.cond7.preheader---%for.cond33.preheader.jscop.transformed @@ -0,0 +1,74 @@ +{ + "arrays" : [ + { + "name" : "MemRef_ATH", + "sizes" : [ "*" ], + "type" : "float" + }, + { + "name" : "MemRef_ath", + "sizes" : [ "*" ], + "type" : "float" + } + ], + "context" : "[p_0] -> { : 0 <= p_0 <= 16 }", + "name" : "%for.cond7.preheader---%for.cond33.preheader", + "statements" : [ + { + "accesses" : [ + { + "kind" : "read", + "relation" : "[p_0] -> { Stmt_for_cond7_preheader[i0] -> MemRef_ATH[0] }" + }, + { + "kind" : "write", + "relation" : "[p_0] -> { Stmt_for_cond7_preheader[i0] -> MemRef_ath[i0] }" + } + ], + "domain" : "[p_0] -> { Stmt_for_cond7_preheader[i0] : 0 <= i0 <= 55 }", + "name" : "Stmt_for_cond7_preheader", + "schedule" : "[p_0] -> { Stmt_for_cond7_preheader[i0] -> [i0, 0] }" + }, + { + "accesses" : [ + { + "kind" : "write", + "relation" : "[p_0] -> { Stmt_if_then_3[i0] -> MemRef_ath[i0] }" + } + ], + "domain" : "[p_0] -> { Stmt_if_then_3[i0] : 0 <= i0 <= 84 - 4p_0 and i0 <= 55 }", + "name" : "Stmt_if_then_3", + "schedule" : "[p_0] -> { Stmt_if_then_3[i0] -> [i0, 2] }" + }, + { + "accesses" : [ + { + "kind" : "read", + "relation" : "[p_0] -> { Stmt_if_else_3[i0] -> MemRef_ath[i0] : i0 >= 0 }" + }, + { + "kind" : "write", + "relation" : "[p_0] -> { Stmt_if_else_3[i0] -> MemRef_ath[i0] : i0 >= 0 }" + } + ], + "domain" : "[p_0] -> { Stmt_if_else_3[i0] : 85 - 4p_0 <= i0 <= 55 }", + "name" : "Stmt_if_else_3", + "schedule" : "[p_0] -> { Stmt_if_else_3[i0] -> [i0, 1] }" + }, + { + "accesses" : [ + { + "kind" : "read", + "relation" : "[p_0] -> { Stmt_for_inc_3[i0] -> MemRef_ath[i0] }" + }, + { + "kind" : "write", + "relation" : "[p_0] -> { Stmt_for_inc_3[i0] -> MemRef_ath[i0] }" + } + ], + "domain" : "[p_0] -> { Stmt_for_inc_3[i0] : 0 <= i0 <= 55 }", + "name" : "Stmt_for_inc_3", + "schedule" : "[p_0] -> { Stmt_for_inc_3[i0] -> [i0, 3] }" + } + ] +} |
