diff options
| -rw-r--r-- | llvm/lib/CodeGen/MachineScheduler.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll | 16 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/sibling-call.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/saxpy10-a9.ll | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsx-fma-m.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/ftrunc.f64.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/local-memory-two-objects.ll | 4 |
8 files changed, 25 insertions, 25 deletions
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 7a3c80bb75d..a52d05fa6fa 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -1036,8 +1036,6 @@ void ScheduleDAGMILive::schedule() { scheduleMI(SU, IsTopNode); - updateQueues(SU, IsTopNode); - if (DFSResult) { unsigned SubtreeID = DFSResult->getSubtreeID(SU); if (!ScheduledTrees.test(SubtreeID)) { @@ -1049,6 +1047,8 @@ void ScheduleDAGMILive::schedule() { // Notify the scheduling strategy after updating the DAG. SchedImpl->schedNode(SU, IsTopNode); + + updateQueues(SU, IsTopNode); } assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone."); diff --git a/llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll b/llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll index 6266d1cc9b3..8784abdadfa 100644 --- a/llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll +++ b/llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll @@ -7,13 +7,13 @@ define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone { ; CHECK-LABEL: bar: ; CHECK: add.2d v[[REG:[0-9]+]], v0, v1 ; CHECK: add d[[REG3:[0-9]+]], d[[REG]], d1 +; CHECK: sub d[[REG2:[0-9]+]], d[[REG]], d1 ; Without advanced copy optimization, we end up with cross register ; banks copies that cannot be coalesced. ; CHECK-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]] ; With advanced copy optimization, we end up with just one copy ; to insert the computed high part into the V register. ; CHECK-OPT-NOT: fmov -; CHECK: sub d[[REG2:[0-9]+]], d[[REG]], d1 ; CHECK: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]] ; CHECK-NOOPT: fmov d0, [[COPY_REG3]] ; CHECK-OPT-NOT: fmov @@ -23,9 +23,9 @@ define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone { ; GENERIC-LABEL: bar: ; GENERIC: add v[[REG:[0-9]+]].2d, v0.2d, v1.2d ; GENERIC: add d[[REG3:[0-9]+]], d[[REG]], d1 +; GENERIC: sub d[[REG2:[0-9]+]], d[[REG]], d1 ; GENERIC-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]] ; GENERIC-OPT-NOT: fmov -; GENERIC: sub d[[REG2:[0-9]+]], d[[REG]], d1 ; GENERIC: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]] ; GENERIC-NOOPT: fmov d0, [[COPY_REG3]] ; GENERIC-OPT-NOT: fmov diff --git a/llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll b/llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll index c6b7d835780..62596adc743 100644 --- a/llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll +++ b/llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll @@ -15,16 +15,16 @@ define <4 x i16> @fptosi_v4f64_to_v4i16(<4 x double>* %ptr) { define <8 x i8> @fptosi_v4f64_to_v4i8(<8 x double>* %ptr) { ; CHECK: fptosi_v4f64_to_v4i8 -; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d -; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d -; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d ; CHECK-DAG: fcvtzs v[[CONV0:[0-9]+]].2d, v0.2d -; CHECK-DAG: xtn v[[NA3:[0-9]+]].2s, v[[CONV3]].2d -; CHECK-DAG: xtn v[[NA2:[0-9]+]].2s, v[[CONV2]].2d -; CHECK-DAG: xtn v[[NA1:[0-9]+]].2s, v[[CONV1]].2d +; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d +; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d +; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d ; CHECK-DAG: xtn v[[NA0:[0-9]+]].2s, v[[CONV0]].2d -; CHECK-DAG: uzp1 v[[TMP1:[0-9]+]].4h, v[[CONV2]].4h, v[[CONV3]].4h -; CHECK-DAG: uzp1 v[[TMP2:[0-9]+]].4h, v[[CONV0]].4h, v[[CONV1]].4h +; CHECK-DAG: xtn v[[NA1:[0-9]+]].2s, v[[CONV1]].2d +; CHECK-DAG: xtn v[[NA2:[0-9]+]].2s, v[[CONV2]].2d +; CHECK-DAG: xtn v[[NA3:[0-9]+]].2s, v[[CONV3]].2d +; CHECK-DAG: uzp1 v[[TMP1:[0-9]+]].4h, v[[CONV1]].4h, v[[CONV0]].4h +; CHECK-DAG: uzp1 v[[TMP2:[0-9]+]].4h, v[[CONV3]].4h, v[[CONV2]].4h ; CHECK: uzp1 v0.8b, v[[TMP2]].8b, v[[TMP1]].8b %tmp1 = load <8 x double>, <8 x double>* %ptr %tmp2 = fptosi <8 x double> %tmp1 to <8 x i8> diff --git a/llvm/test/CodeGen/AArch64/sibling-call.ll b/llvm/test/CodeGen/AArch64/sibling-call.ll index 34d45d8fb98..a68fdec4cfb 100644 --- a/llvm/test/CodeGen/AArch64/sibling-call.ll +++ b/llvm/test/CodeGen/AArch64/sibling-call.ll @@ -75,8 +75,8 @@ define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) { ; CHECK: ldr [[VAL0:x[0-9]+]], ; CHECK: ldr [[VAL1:x[0-9]+]], -; CHECK: str [[VAL1]], ; CHECK: str [[VAL0]], +; CHECK: str [[VAL1]], ; CHECK-NOT: add sp, sp, ; CHECK: b callee_stack16 diff --git a/llvm/test/CodeGen/ARM/saxpy10-a9.ll b/llvm/test/CodeGen/ARM/saxpy10-a9.ll index af7b7ad5510..91610f1a232 100644 --- a/llvm/test/CodeGen/ARM/saxpy10-a9.ll +++ b/llvm/test/CodeGen/ARM/saxpy10-a9.ll @@ -14,15 +14,12 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- ; CHECK: vldr ; CHECK: vldr ; CHECK: vldr -; CHECK: vldr +; CHECK-NEXT: vldr +; CHECK-NEXT: vmul ; CHECK-NEXT: vadd ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vldr -; CHECK-NEXT: vldr -; CHECK-NEXT: vadd -; CHECK-NEXT: vmul -; CHECK-NEXT: vldr ; CHECK-NEXT: vadd ; CHECK-NEXT: vadd ; CHECK-NEXT: vmul @@ -31,6 +28,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul +; CHECK-NEXT: vldr ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vadd @@ -48,6 +46,8 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr +; CHECK-NEXT: vadd +; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr diff --git a/llvm/test/CodeGen/PowerPC/vsx-fma-m.ll b/llvm/test/CodeGen/PowerPC/vsx-fma-m.ll index 64185a47266..d85927396e3 100644 --- a/llvm/test/CodeGen/PowerPC/vsx-fma-m.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-fma-m.ll @@ -98,9 +98,9 @@ entry: ; re-ordering the instructions. ; CHECK-DAG: xsmaddadp [[F1]], 2, 3 -; CHECK-DAG: xsmaddmdp 2, 3, 4 +; CHECK-DAG: xsmaddmdp 3, 2, 4 ; CHECK-DAG: stxsdx [[F1]], 0, 8 -; CHECK-DAG: stxsdx 2, 8, [[C1]] +; CHECK-DAG: stxsdx 3, 8, [[C1]] ; CHECK-DAG: stxsdx 1, 8, [[C2]] ; CHECK-DAG: stxsdx 4, 8, [[C3]] ; CHECK: blr @@ -269,10 +269,10 @@ entry: ; re-ordering the instructions. ; CHECK-DAG: xvmaddadp [[V1]], 35, 36 -; CHECK-DAG: xvmaddmdp 35, 36, 37 +; CHECK-DAG: xvmaddmdp 36, 35, 37 ; CHECK-DAG: xvmaddadp 34, 35, 38 ; CHECK-DAG: stxvd2x 32, 0, 3 -; CHECK-DAG: stxvd2x 35, 3, [[C1]] +; CHECK-DAG: stxvd2x 36, 3, [[C1]] ; CHECK-DAG: stxvd2x 34, 3, [[C2]] ; CHECK-DAG: stxvd2x 37, 3, [[C3]] ; CHECK: blr diff --git a/llvm/test/CodeGen/R600/ftrunc.f64.ll b/llvm/test/CodeGen/R600/ftrunc.f64.ll index 4ea84a7ea4b..6618d8b5e57 100644 --- a/llvm/test/CodeGen/R600/ftrunc.f64.ll +++ b/llvm/test/CodeGen/R600/ftrunc.f64.ll @@ -27,9 +27,9 @@ define void @v_ftrunc_f64(double addrspace(1)* %out, double addrspace(1)* %in) { ; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 ; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01 ; SI: s_lshr_b64 -; SI: cmp_gt_i32 ; SI: s_not_b64 ; SI: s_and_b64 +; SI: cmp_gt_i32 ; SI: cndmask_b32 ; SI: cndmask_b32 ; SI: cmp_lt_i32 diff --git a/llvm/test/CodeGen/R600/local-memory-two-objects.ll b/llvm/test/CodeGen/R600/local-memory-two-objects.ll index caa4b19cd88..06a8b1246e6 100644 --- a/llvm/test/CodeGen/R600/local-memory-two-objects.ll +++ b/llvm/test/CodeGen/R600/local-memory-two-objects.ll @@ -32,8 +32,8 @@ ; EG-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]] ; SI: v_add_i32_e32 [[SIPTR:v[0-9]+]], 16, v{{[0-9]+}} ; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]] -; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] -; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]] offset:16 +; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] offset:16 +; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]] define void @local_memory_two_objects(i32 addrspace(1)* %out) { entry: |
