diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index da9adcb50fb..5448c28c6da 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -34517,6 +34517,7 @@ static SDValue combineFMA(SDNode *N, SelectionDAG &DAG, // Negative multiplication when NegA xor NegB bool NegMul = (NegA != NegB); + bool HasNeg = NegA || NegB || NegC; unsigned NewOpcode; if (!NegMul) @@ -34524,6 +34525,14 @@ static SDValue combineFMA(SDNode *N, SelectionDAG &DAG, else NewOpcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB; + // For FMA and FAMDD, we risk reconstructing the node we started with. + // In order to avoid this, we check for negation or opcode change. If + // one of the two happened, then it is a new node and we return it. + if (N->getOpcode() == X86ISD::FMADD || N->getOpcode() == ISD::FMA) { + if (HasNeg || NewOpcode != N->getOpcode()) + return DAG.getNode(NewOpcode, dl, VT, A, B, C); + return SDValue(); + } if (N->getOpcode() == X86ISD::FMADD_RND) { switch (NewOpcode) { @@ -34547,12 +34556,15 @@ static SDValue combineFMA(SDNode *N, SelectionDAG &DAG, case X86ISD::FNMSUB: NewOpcode = X86ISD::FNMSUBS3_RND; break; } } else { - assert((N->getOpcode() == X86ISD::FMADD || N->getOpcode() == ISD::FMA) && - "Unexpected opcode!"); - return DAG.getNode(NewOpcode, dl, VT, A, B, C); + llvm_unreachable("Unexpected opcode!"); } - return DAG.getNode(NewOpcode, dl, VT, A, B, C, N->getOperand(3)); + // Only return the node is the opcode was changed or one of the + // operand was negated. If not, we'll just recreate the same node. + if (HasNeg || NewOpcode != N->getOpcode()) + return DAG.getNode(NewOpcode, dl, VT, A, B, C, N->getOperand(3)); + + return SDValue(); } static SDValue combineZext(SDNode *N, SelectionDAG &DAG, |
