diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 3 |
3 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp index 2cb3d8fbd1e..73e9e2f4dbc 100644 --- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp +++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp @@ -1795,7 +1795,6 @@ void ISel::Select(SDOperand N) { } else { //ISD::TRUNCSTORE switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) { default: assert(0 && "unknown Type in store"); - case MVT::i1: case MVT::i8: Opc = PPC::STB; break; case MVT::i16: Opc = PPC::STH; break; } diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 0ae7ad6b4fb..e342d71921e 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -1263,7 +1263,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) { } else { //ISD::TRUNCSTORE switch(cast<VTSDNode>(N->getOperand(4))->getVT()) { default: assert(0 && "unknown Type in store"); - case MVT::i1: case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break; case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break; } diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index bf8dbed006d..340c0a478ad 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -91,6 +91,9 @@ PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM) setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); + // PowerPC does not have truncstore for i1. + setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); + // 64 bit PowerPC implementations have instructions to facilitate conversion // between i64 and fp. if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { |
