diff options
| -rw-r--r-- | llvm/include/llvm/Target/TargetInstrInfo.h | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 23 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.h | 2 |
4 files changed, 34 insertions, 1 deletions
diff --git a/llvm/include/llvm/Target/TargetInstrInfo.h b/llvm/include/llvm/Target/TargetInstrInfo.h index af0fc803a75..920a52daa7f 100644 --- a/llvm/include/llvm/Target/TargetInstrInfo.h +++ b/llvm/include/llvm/Target/TargetInstrInfo.h @@ -1481,6 +1481,11 @@ public: return None; } + /// Determines whether |Inst| is a tail call instruction. + virtual bool isTailCall(const MachineInstr &Inst) const { + return false; + } + private: unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode; unsigned CatchRetOpcode; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 4715a4ffcc3..fcb3f037354 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -340,7 +340,10 @@ public: bool isSignExtendingLoad(const MachineInstr &MI) const; bool isSolo(const MachineInstr &MI) const; bool isSpillPredRegOp(const MachineInstr &MI) const; - bool isTailCall(const MachineInstr &MI) const; + + // Defined in Target.h. + bool isTailCall(const MachineInstr &MI) const override; + bool isTC1(const MachineInstr &MI) const; bool isTC2(const MachineInstr &MI) const; bool isTC2Early(const MachineInstr &MI) const; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 0ba6dd85c6f..ee5ebfd6dba 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -8061,6 +8061,29 @@ X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const { return makeArrayRef(TargetFlags); } +bool X86InstrInfo::isTailCall(const MachineInstr &Inst) const { + switch (Inst.getOpcode()) { + case X86::TCRETURNdi: + case X86::TCRETURNmi: + case X86::TCRETURNri: + case X86::TCRETURNdi64: + case X86::TCRETURNmi64: + case X86::TCRETURNri64: + case X86::TAILJMPd: + case X86::TAILJMPm: + case X86::TAILJMPr: + case X86::TAILJMPd64: + case X86::TAILJMPm64: + case X86::TAILJMPr64: + case X86::TAILJMPd64_REX: + case X86::TAILJMPm64_REX: + case X86::TAILJMPr64_REX: + return true; + default: + return false; + } +} + namespace { /// Create Global Base Reg pass. This initializes the PIC /// global base register for x86-32. diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index 5c8de0fe281..5fff2a3ac7d 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -541,6 +541,8 @@ public: ArrayRef<std::pair<unsigned, const char *>> getSerializableDirectMachineOperandTargetFlags() const override; + bool isTailCall(const MachineInstr &Inst) const override; + protected: /// Commutes the operands in the given instruction by changing the operands /// order and/or changing the instruction's opcode and/or the immediate value |
