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-rw-r--r--llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td42
-rw-r--r--llvm/lib/Target/Mips/MipsDSPInstrInfo.td20
-rw-r--r--llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt10
-rw-r--r--llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt10
-rw-r--r--llvm/test/MC/Mips/micromips-dsp/valid.s10
-rw-r--r--llvm/test/MC/Mips/micromips-dspr2/valid.s10
6 files changed, 92 insertions, 10 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
index 15d571a56d8..3ac418219d5 100644
--- a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
@@ -67,6 +67,16 @@ class SHRL_PH_MMR2_ENC : POOL32A_2RSA4OP6_FMT<"shrl.ph", 0b001111>;
class SHRL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shrl.qb", 0b1100001>;
class SHRLV_PH_MMR2_ENC : POOL32A_3RB0_FMT<"shrlv.ph", 0b1100010101>;
class SHRLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shrlv.qb", 0b1101010101>;
+class PRECEQ_W_PHL_MM_ENC : POOL32A_2R_FMT<"preceq.w.phl", 0b0101000100>;
+class PRECEQ_W_PHR_MM_ENC : POOL32A_2R_FMT<"preceq.w.phr", 0b0110000100>;
+class PRECEQU_PH_QBL_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbl", 0b0111000100>;
+class PRECEQU_PH_QBLA_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbla", 0b0111001100>;
+class PRECEQU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbr", 0b1001000100>;
+class PRECEQU_PH_QBRA_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbra", 0b1001001100>;
+class PRECEU_PH_QBL_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbl", 0b1011000100>;
+class PRECEU_PH_QBLA_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbla", 0b1011001100>;
+class PRECEU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbr", 0b1101000100>;
+class PRECEU_PH_QBRA_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbra", 0b1101001100>;
// Instruction desc.
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
@@ -84,6 +94,26 @@ class ABSQ_S_W_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>;
class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
+class PRECEQ_W_PHL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
+ "preceq.w.phl", int_mips_preceq_w_phl, NoItinerary, GPR32Opnd, DSPROpnd>;
+class PRECEQ_W_PHR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
+ "preceq.w.phr", int_mips_preceq_w_phr, NoItinerary, GPR32Opnd, DSPROpnd>;
+class PRECEQU_PH_QBL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
+ "precequ.ph.qbl", int_mips_precequ_ph_qbl, NoItinerary, DSPROpnd>;
+class PRECEQU_PH_QBLA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
+ "precequ.ph.qbla", int_mips_precequ_ph_qbla, NoItinerary, DSPROpnd>;
+class PRECEQU_PH_QBR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
+ "precequ.ph.qbr", int_mips_precequ_ph_qbr, NoItinerary, DSPROpnd>;
+class PRECEQU_PH_QBRA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
+ "precequ.ph.qbra", int_mips_precequ_ph_qbra, NoItinerary, DSPROpnd>;
+class PRECEU_PH_QBL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
+ "preceu.ph.qbl", int_mips_preceu_ph_qbl, NoItinerary, DSPROpnd>;
+class PRECEU_PH_QBLA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
+ "preceu.ph.qbla", int_mips_preceu_ph_qbla, NoItinerary, DSPROpnd>;
+class PRECEU_PH_QBR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
+ "preceu.ph.qbr", int_mips_preceu_ph_qbr, NoItinerary, DSPROpnd>;
+class PRECEU_PH_QBRA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
+ "preceu.ph.qbra", int_mips_preceu_ph_qbra, NoItinerary, DSPROpnd>;
class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
SDPatternOperator ImmPat, InstrItinClass itin,
@@ -192,6 +222,18 @@ def SHRAV_R_W_MM : DspMMRel, SHRAV_R_W_MM_ENC, SHRAV_R_W_MM_DESC;
def SHRA_R_W_MM : DspMMRel, SHRA_R_W_MM_ENC, SHRA_R_W_MM_DESC;
def SHRL_QB_MM : DspMMRel, SHRL_QB_MM_ENC, SHRL_QB_MM_DESC;
def SHRLV_QB_MM : DspMMRel, SHRLV_QB_MM_ENC, SHRLV_QB_MM_DESC;
+def PRECEQ_W_PHL_MM : DspMMRel, PRECEQ_W_PHL_MM_ENC, PRECEQ_W_PHL_MM_DESC;
+def PRECEQ_W_PHR_MM : DspMMRel, PRECEQ_W_PHR_MM_ENC, PRECEQ_W_PHR_MM_DESC;
+def PRECEQU_PH_QBL_MM : DspMMRel, PRECEQU_PH_QBL_MM_ENC, PRECEQU_PH_QBL_MM_DESC;
+def PRECEQU_PH_QBLA_MM : DspMMRel, PRECEQU_PH_QBLA_MM_ENC,
+ PRECEQU_PH_QBLA_MM_DESC;
+def PRECEQU_PH_QBR_MM : DspMMRel, PRECEQU_PH_QBR_MM_ENC, PRECEQU_PH_QBR_MM_DESC;
+def PRECEQU_PH_QBRA_MM : DspMMRel, PRECEQU_PH_QBRA_MM_ENC,
+ PRECEQU_PH_QBRA_MM_DESC;
+def PRECEU_PH_QBL_MM : DspMMRel, PRECEU_PH_QBL_MM_ENC, PRECEU_PH_QBL_MM_DESC;
+def PRECEU_PH_QBLA_MM : DspMMRel, PRECEU_PH_QBLA_MM_ENC, PRECEU_PH_QBLA_MM_DESC;
+def PRECEU_PH_QBR_MM : DspMMRel, PRECEU_PH_QBR_MM_ENC, PRECEU_PH_QBR_MM_DESC;
+def PRECEU_PH_QBRA_MM : DspMMRel, PRECEU_PH_QBRA_MM_ENC, PRECEU_PH_QBRA_MM_DESC;
// microMIPS DSP Rev 2
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
ISA_DSPR2;
diff --git a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
index 49184f1f881..e6dd167ee9c 100644
--- a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
@@ -1107,16 +1107,16 @@ def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
-def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
-def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
-def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
-def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
-def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
-def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
-def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
-def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
-def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
-def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
+def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
+def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
+def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
+def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
+def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
+def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
+def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
+def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
+def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
+def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
diff --git a/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
index 46553cc7318..c5f90bf0426 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
@@ -20,6 +20,16 @@
0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3
0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5
+0x00 0x22 0x51 0x3c # CHECK: preceq.w.phl $1, $2
+0x00 0x64 0x61 0x3c # CHECK: preceq.w.phr $3, $4
+0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6
+0x00 0xe8 0x73 0x3c # CHECK: precequ.ph.qbla $7, $8
+0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10
+0x01 0x6c 0x93 0x3c # CHECK: precequ.ph.qbra $11, $12
+0x01 0xae 0xb1 0x3c # CHECK: preceu.ph.qbl $13, $14
+0x01 0xf0 0xb3 0x3c # CHECK: preceu.ph.qbla $15, $16
+0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18
+0x02 0x74 0xd3 0x3c # CHECK: preceu.ph.qbra $19, $20
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
diff --git a/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
index b1fa321b157..bf43e286101 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
@@ -33,6 +33,16 @@
0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3
0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5
+0x00 0x22 0x51 0x3c # CHECK: preceq.w.phl $1, $2
+0x00 0x64 0x61 0x3c # CHECK: preceq.w.phr $3, $4
+0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6
+0x00 0xe8 0x73 0x3c # CHECK: precequ.ph.qbla $7, $8
+0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10
+0x01 0x6c 0x93 0x3c # CHECK: precequ.ph.qbra $11, $12
+0x01 0xae 0xb1 0x3c # CHECK: preceu.ph.qbl $13, $14
+0x01 0xf0 0xb3 0x3c # CHECK: preceu.ph.qbla $15, $16
+0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18
+0x02 0x74 0xd3 0x3c # CHECK: preceu.ph.qbra $19, $20
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
diff --git a/llvm/test/MC/Mips/micromips-dsp/valid.s b/llvm/test/MC/Mips/micromips-dsp/valid.s
index f0b245d179e..1d7c430fbb0 100644
--- a/llvm/test/MC/Mips/micromips-dsp/valid.s
+++ b/llvm/test/MC/Mips/micromips-dsp/valid.s
@@ -21,6 +21,16 @@
msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc]
mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc]
multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]
+ preceq.w.phl $1, $2 # CHECK: preceq.w.phl $1, $2 # encoding: [0x00,0x22,0x51,0x3c]
+ preceq.w.phr $3, $4 # CHECK: preceq.w.phr $3, $4 # encoding: [0x00,0x64,0x61,0x3c]
+ precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c]
+ precequ.ph.qbla $7, $8 # CHECK: precequ.ph.qbla $7, $8 # encoding: [0x00,0xe8,0x73,0x3c]
+ precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c]
+ precequ.ph.qbra $11, $12 # CHECK: precequ.ph.qbra $11, $12 # encoding: [0x01,0x6c,0x93,0x3c]
+ preceu.ph.qbl $13, $14 # CHECK: preceu.ph.qbl $13, $14 # encoding: [0x01,0xae,0xb1,0x3c]
+ preceu.ph.qbla $15, $16 # CHECK: preceu.ph.qbla $15, $16 # encoding: [0x01,0xf0,0xb3,0x3c]
+ preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
+ preceu.ph.qbra $19, $20 # CHECK: preceu.ph.qbra $19, $20 # encoding: [0x02,0x74,0xd3,0x3c]
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]
diff --git a/llvm/test/MC/Mips/micromips-dspr2/valid.s b/llvm/test/MC/Mips/micromips-dspr2/valid.s
index c35607f2ccb..fd4586cba34 100644
--- a/llvm/test/MC/Mips/micromips-dspr2/valid.s
+++ b/llvm/test/MC/Mips/micromips-dspr2/valid.s
@@ -34,6 +34,16 @@
msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc]
mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc]
multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]
+ preceq.w.phl $1, $2 # CHECK: preceq.w.phl $1, $2 # encoding: [0x00,0x22,0x51,0x3c]
+ preceq.w.phr $3, $4 # CHECK: preceq.w.phr $3, $4 # encoding: [0x00,0x64,0x61,0x3c]
+ precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c]
+ precequ.ph.qbla $7, $8 # CHECK: precequ.ph.qbla $7, $8 # encoding: [0x00,0xe8,0x73,0x3c]
+ precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c]
+ precequ.ph.qbra $11, $12 # CHECK: precequ.ph.qbra $11, $12 # encoding: [0x01,0x6c,0x93,0x3c]
+ preceu.ph.qbl $13, $14 # CHECK: preceu.ph.qbl $13, $14 # encoding: [0x01,0xae,0xb1,0x3c]
+ preceu.ph.qbla $15, $16 # CHECK: preceu.ph.qbla $15, $16 # encoding: [0x01,0xf0,0xb3,0x3c]
+ preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
+ preceu.ph.qbra $19, $20 # CHECK: preceu.ph.qbra $19, $20 # encoding: [0x02,0x74,0xd3,0x3c]
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]
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