diff options
| -rw-r--r-- | llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/NVPTX/f16-instructions.ll | 15 |
2 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 0fd8d4b2aa7..48954fd19e5 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -332,6 +332,8 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM, setOperationAction(ISD::FSUB, MVT::f16, Promote); setOperationAction(ISD::FMA, MVT::f16, Promote); } + // There's no neg.f16 instruction. + setOperationAction(ISD::FNEG, MVT::f16, Expand); // Library functions. These default to Expand, but we have instructions // for them. diff --git a/llvm/test/CodeGen/NVPTX/f16-instructions.ll b/llvm/test/CodeGen/NVPTX/f16-instructions.ll index 2ae7923a3a7..b94fd17e91f 100644 --- a/llvm/test/CodeGen/NVPTX/f16-instructions.ll +++ b/llvm/test/CodeGen/NVPTX/f16-instructions.ll @@ -80,6 +80,21 @@ define half @test_fsub(half %a, half %b) #0 { ret half %r } +; CHECK-LABEL: test_fneg( +; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fneg_param_0]; +; CHECK-F16-NEXT: mov.b16 [[Z:%h[0-9]+]], 0x0000 +; CHECK-F16-NEXT: sub.rn.f16 [[R:%h[0-9]+]], [[Z]], [[A]]; +; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]] +; CHECK-NOF16-DAG: mov.f32 [[Z:%f[0-9]+]], 0f00000000; +; CHECK-NOF16-NEXT: sub.rn.f32 [[R32:%f[0-9]+]], [[Z]], [[A32]]; +; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] +; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; +; CHECK-NEXT: ret; +define half @test_fneg(half %a) #0 { + %r = fsub half 0.0, %a + ret half %r +} + ; CHECK-LABEL: test_fmul( ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fmul_param_0]; ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fmul_param_1]; |
