diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleA9.td | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/saxpy10-a9.ll | 20 |
2 files changed, 18 insertions, 12 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleA9.td b/llvm/lib/Target/ARM/ARMScheduleA9.td index e4c2c753aec..9a1d2227564 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA9.td +++ b/llvm/lib/Target/ARM/ARMScheduleA9.td @@ -1902,14 +1902,20 @@ def CortexA9Model : SchedMachineModel { //===----------------------------------------------------------------------===// // Define each kind of processor resource and number available. +// +// The AGU unit has BufferSize=1 so that the latency between operations +// that use it are considered to stall other operations. +// +// The FP unit has BufferSize=0 so that it is a hard dispatch +// hazard. No instruction may be dispatched while the unit is reserved. let SchedModel = CortexA9Model in { def A9UnitALU : ProcResource<2>; def A9UnitMul : ProcResource<1> { let Super = A9UnitALU; } -def A9UnitAGU : ProcResource<1>; +def A9UnitAGU : ProcResource<1> { let BufferSize = 1; } def A9UnitLS : ProcResource<1>; -def A9UnitFP : ProcResource<1> { let BufferSize = 1; } +def A9UnitFP : ProcResource<1> { let BufferSize = 0; } def A9UnitB : ProcResource<1>; //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/ARM/saxpy10-a9.ll b/llvm/test/CodeGen/ARM/saxpy10-a9.ll index 1102800dce0..f8f5e18fcf5 100644 --- a/llvm/test/CodeGen/ARM/saxpy10-a9.ll +++ b/llvm/test/CodeGen/ARM/saxpy10-a9.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -disable-post-ra -misched-bench -scheditins=false | FileCheck %s +; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -misched-postra -misched-bench -scheditins=false | FileCheck %s ; ; Test MI-Sched suppory latency based stalls on in in-order pipeline ; using the new machine model. @@ -15,43 +15,43 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- ; CHECK: vldr ; CHECK: vldr ; CHECK: vldr -; CHECK-NEXT: vmul ; CHECK-NEXT: vadd ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vldr +; CHECK-NEXT: vldr +; CHECK-NEXT: vadd ; CHECK-NEXT: vmul +; CHECK-NEXT: vldr ; CHECK-NEXT: vadd ; CHECK-NEXT: vadd -; CHECK-NEXT: vldr -; CHECK-NEXT: vldr ; CHECK-NEXT: vmul +; CHECK-NEXT: vldr ; CHECK-NEXT: vadd ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr -; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd -; CHECK-NEXT: vadd ; CHECK-NEXT: vldr +; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd -; CHECK-NEXT: vadd ; CHECK-NEXT: vldr +; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd -; CHECK-NEXT: vadd ; CHECK-NEXT: vldr +; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd -; CHECK-NEXT: vadd -; CHECK-NEXT: vldr ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd +; CHECK-NEXT: vldr +; CHECK-NEXT: vmul ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vadd |
