diff options
| -rw-r--r-- | llvm/include/llvm/Target/TargetSchedule.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedA53.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedM1.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleA8.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/Lanai/LanaiSchedule.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCSchedule440.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleA2.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleE500mc.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleE5500.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleG5.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleP7.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleP8.td | 1 |
12 files changed, 0 insertions, 16 deletions
diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td index 91dc3b4fca4..7f92e8b6556 100644 --- a/llvm/include/llvm/Target/TargetSchedule.td +++ b/llvm/include/llvm/Target/TargetSchedule.td @@ -76,8 +76,6 @@ def instregex; // See MCSchedule.h for detailed comments. class SchedMachineModel { int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle. - int MinLatency = -1; // Determines which instructions are allowed in a group. - // (-1) inorder (0) ooo, (1): inorder +var latencies. int MicroOpBufferSize = -1; // Max micro-ops that can be buffered. int LoopMicroOpBufferSize = -1; // Max micro-ops that can be buffered for // optimized loop dispatch/execution. diff --git a/llvm/lib/Target/AArch64/AArch64SchedA53.td b/llvm/lib/Target/AArch64/AArch64SchedA53.td index b8ad1451e11..93ca079275c 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedA53.td +++ b/llvm/lib/Target/AArch64/AArch64SchedA53.td @@ -19,7 +19,6 @@ def CortexA53Model : SchedMachineModel { let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order. let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. - let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency. let LoadLatency = 3; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. diff --git a/llvm/lib/Target/AArch64/AArch64SchedM1.td b/llvm/lib/Target/AArch64/AArch64SchedM1.td index f2bada2f764..da403006181 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedM1.td +++ b/llvm/lib/Target/AArch64/AArch64SchedM1.td @@ -19,7 +19,6 @@ def ExynosM1Model : SchedMachineModel { let IssueWidth = 4; // Up to 4 uops per cycle. - let MinLatency = 0; // OoO. let MicroOpBufferSize = 96; // ROB size. let LoopMicroOpBufferSize = 32; // Instruction queue size. let LoadLatency = 4; // Optimistic load cases. diff --git a/llvm/lib/Target/ARM/ARMScheduleA8.td b/llvm/lib/Target/ARM/ARMScheduleA8.td index 154a889b41a..ba380cba100 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA8.td +++ b/llvm/lib/Target/ARM/ARMScheduleA8.td @@ -1065,7 +1065,6 @@ def CortexA8Itineraries : ProcessorItineraries< // Cortex-A8 machine model for scheduling and other instruction cost heuristics. def CortexA8Model : SchedMachineModel { let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. - let MinLatency = -1; // OperandCycles are interpreted as MinLatency. let LoadLatency = 2; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. diff --git a/llvm/lib/Target/Lanai/LanaiSchedule.td b/llvm/lib/Target/Lanai/LanaiSchedule.td index 72c22a6b30c..7f931c4be8b 100644 --- a/llvm/lib/Target/Lanai/LanaiSchedule.td +++ b/llvm/lib/Target/Lanai/LanaiSchedule.td @@ -39,10 +39,6 @@ def LanaiSchedModel : SchedMachineModel { // Max micro-ops that may be scheduled per cycle. [default = 1] let IssueWidth = 1; - // Determines which instructions are allowed in a group. 1 is an inorder - // CPU with variable latencies. [default = -1] - let MinLatency = 1; - // Extra cycles for a mispredicted branch. [default = -1] let MispredictPenalty = 10; diff --git a/llvm/lib/Target/PowerPC/PPCSchedule440.td b/llvm/lib/Target/PowerPC/PPCSchedule440.td index e4a2c3b474d..2455e5e52de 100644 --- a/llvm/lib/Target/PowerPC/PPCSchedule440.td +++ b/llvm/lib/Target/PowerPC/PPCSchedule440.td @@ -597,7 +597,6 @@ def PPC440Itineraries : ProcessorItineraries< def PPC440Model : SchedMachineModel { let IssueWidth = 2; // 2 instructions are dispatched per cycle. - let MinLatency = -1; // OperandCycles are interpreted as MinLatency. let LoadLatency = 5; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td index 7cab1b2d462..54cfae5d74b 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td @@ -160,7 +160,6 @@ def PPCA2Itineraries : ProcessorItineraries< def PPCA2Model : SchedMachineModel { let IssueWidth = 1; // 1 instruction is dispatched per cycle. - let MinLatency = -1; // OperandCycles are interpreted as MinLatency. let LoadLatency = 6; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td b/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td index 95e5ab64ed5..f687d326b52 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td @@ -311,7 +311,6 @@ def PPCE500mcItineraries : ProcessorItineraries< def PPCE500mcModel : SchedMachineModel { let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. - let MinLatency = -1; // OperandCycles are interpreted as MinLatency. let LoadLatency = 5; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE5500.td b/llvm/lib/Target/PowerPC/PPCScheduleE5500.td index d3673c0158e..5db886cf8f9 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleE5500.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleE5500.td @@ -371,7 +371,6 @@ def PPCE5500Itineraries : ProcessorItineraries< def PPCE5500Model : SchedMachineModel { let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. - let MinLatency = -1; // OperandCycles are interpreted as MinLatency. let LoadLatency = 6; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. diff --git a/llvm/lib/Target/PowerPC/PPCScheduleG5.td b/llvm/lib/Target/PowerPC/PPCScheduleG5.td index b2c2bd23c12..b5a9f96d45a 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleG5.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleG5.td @@ -118,7 +118,6 @@ def G5Itineraries : ProcessorItineraries< def G5Model : SchedMachineModel { let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle. - let MinLatency = 0; // Out-of-order dispatch. let LoadLatency = 3; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP7.td b/llvm/lib/Target/PowerPC/PPCScheduleP7.td index 26c80c92c90..a8678f56900 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleP7.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleP7.td @@ -382,7 +382,6 @@ def P7Model : SchedMachineModel { // branches), but the total internal issue bandwidth per // cycle (from all queues) is 8. - let MinLatency = 0; // Out-of-order dispatch. let LoadLatency = 3; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP8.td b/llvm/lib/Target/PowerPC/PPCScheduleP8.td index b7083e6bafe..8e52da583a0 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleP8.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleP8.td @@ -391,7 +391,6 @@ def P8Model : SchedMachineModel { // up to six non-branch instructions. // up to two branches in a dispatch group. - let MinLatency = 0; // Out-of-order dispatch. let LoadLatency = 3; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. |
