diff options
4 files changed, 80 insertions, 54 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index a6280ec95a9..7e7a515bfc8 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -1831,14 +1831,33 @@ static bool areInverseVectorBitmasks(Constant *C1, Constant *C2) { /// We have an expression of the form (A & C) | (B & D). If A is a scalar or /// vector composed of all-zeros or all-ones values and is the bitwise 'not' of /// B, it can be used as the condition operand of a select instruction. -static Value *getSelectCondition(Value *A, Value *B, - InstCombiner::BuilderTy &Builder) { - // If these are scalars or vectors of i1, A can be used directly. +Value *InstCombiner::getSelectCondition(Value *A, Value *B) { + // Step 1: We may have peeked through bitcasts in the caller. + // Exit immediately if we don't have (vector) integer types. Type *Ty = A->getType(); - if (match(A, m_Not(m_Specific(B))) && Ty->isIntOrIntVectorTy(1)) - return A; + if (!Ty->isIntOrIntVectorTy() || !B->getType()->isIntOrIntVectorTy()) + return nullptr; + + // Step 2: We need 0 or all-1's bitmasks. + if (ComputeNumSignBits(A) != Ty->getScalarSizeInBits()) + return nullptr; - // If A and B are sign-extended, look through the sexts to find the booleans. + // Step 3: If B is the 'not' value of A, we have our answer. + if (match(A, m_Not(m_Specific(B)))) { + // If these are scalars or vectors of i1, A can be used directly. + if (Ty->isIntOrIntVectorTy(1)) + return A; + return Builder.CreateTrunc(A, CmpInst::makeCmpResultType(Ty)); + } + + // If both operands are constants, see if the constants are inverse bitmasks. + Constant *AConst, *BConst; + if (match(A, m_Constant(AConst)) && match(B, m_Constant(BConst))) + if (AConst == ConstantExpr::getNot(BConst)) + return Builder.CreateZExtOrTrunc(A, CmpInst::makeCmpResultType(Ty)); + + // Look for more complex patterns. The 'not' op may be hidden behind various + // casts. Look through sexts and bitcasts to find the booleans. Value *Cond; Value *NotB; if (match(A, m_SExt(m_Value(Cond))) && @@ -1854,36 +1873,29 @@ static Value *getSelectCondition(Value *A, Value *B, if (!Ty->isVectorTy()) return nullptr; - // If both operands are constants, see if the constants are inverse bitmasks. - Constant *AC, *BC; - if (match(A, m_Constant(AC)) && match(B, m_Constant(BC)) && - areInverseVectorBitmasks(AC, BC)) { - return Builder.CreateZExtOrTrunc(AC, CmpInst::makeCmpResultType(Ty)); - } - // If both operands are xor'd with constants using the same sexted boolean // operand, see if the constants are inverse bitmasks. - if (match(A, (m_Xor(m_SExt(m_Value(Cond)), m_Constant(AC)))) && - match(B, (m_Xor(m_SExt(m_Specific(Cond)), m_Constant(BC)))) && + // TODO: Use ConstantExpr::getNot()? + if (match(A, (m_Xor(m_SExt(m_Value(Cond)), m_Constant(AConst)))) && + match(B, (m_Xor(m_SExt(m_Specific(Cond)), m_Constant(BConst)))) && Cond->getType()->isIntOrIntVectorTy(1) && - areInverseVectorBitmasks(AC, BC)) { - AC = ConstantExpr::getTrunc(AC, CmpInst::makeCmpResultType(Ty)); - return Builder.CreateXor(Cond, AC); + areInverseVectorBitmasks(AConst, BConst)) { + AConst = ConstantExpr::getTrunc(AConst, CmpInst::makeCmpResultType(Ty)); + return Builder.CreateXor(Cond, AConst); } return nullptr; } /// We have an expression of the form (A & C) | (B & D). Try to simplify this /// to "A' ? C : D", where A' is a boolean or vector of booleans. -static Value *matchSelectFromAndOr(Value *A, Value *C, Value *B, Value *D, - InstCombiner::BuilderTy &Builder) { +Value *InstCombiner::matchSelectFromAndOr(Value *A, Value *C, Value *B, + Value *D) { // The potential condition of the select may be bitcasted. In that case, look // through its bitcast and the corresponding bitcast of the 'not' condition. Type *OrigType = A->getType(); A = peekThroughBitcast(A, true); B = peekThroughBitcast(B, true); - - if (Value *Cond = getSelectCondition(A, B, Builder)) { + if (Value *Cond = getSelectCondition(A, B)) { // ((bc Cond) & C) | ((bc ~Cond) & D) --> bc (select Cond, (bc C), (bc D)) // The bitcasts will either all exist or all not exist. The builder will // not create unnecessary casts if the types already match. @@ -2234,21 +2246,21 @@ Instruction *InstCombiner::visitOr(BinaryOperator &I) { // 'or' that it is replacing. if (Op0->hasOneUse() || Op1->hasOneUse()) { // (Cond & C) | (~Cond & D) -> Cond ? C : D, and commuted variants. - if (Value *V = matchSelectFromAndOr(A, C, B, D, Builder)) + if (Value *V = matchSelectFromAndOr(A, C, B, D)) return replaceInstUsesWith(I, V); - if (Value *V = matchSelectFromAndOr(A, C, D, B, Builder)) + if (Value *V = matchSelectFromAndOr(A, C, D, B)) return replaceInstUsesWith(I, V); - if (Value *V = matchSelectFromAndOr(C, A, B, D, Builder)) + if (Value *V = matchSelectFromAndOr(C, A, B, D)) return replaceInstUsesWith(I, V); - if (Value *V = matchSelectFromAndOr(C, A, D, B, Builder)) + if (Value *V = matchSelectFromAndOr(C, A, D, B)) return replaceInstUsesWith(I, V); - if (Value *V = matchSelectFromAndOr(B, D, A, C, Builder)) + if (Value *V = matchSelectFromAndOr(B, D, A, C)) return replaceInstUsesWith(I, V); - if (Value *V = matchSelectFromAndOr(B, D, C, A, Builder)) + if (Value *V = matchSelectFromAndOr(B, D, C, A)) return replaceInstUsesWith(I, V); - if (Value *V = matchSelectFromAndOr(D, B, A, C, Builder)) + if (Value *V = matchSelectFromAndOr(D, B, A, C)) return replaceInstUsesWith(I, V); - if (Value *V = matchSelectFromAndOr(D, B, C, A, Builder)) + if (Value *V = matchSelectFromAndOr(D, B, C, A)) return replaceInstUsesWith(I, V); } } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h index a4d7fe8861b..431856c9e00 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h +++ b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h @@ -589,6 +589,9 @@ private: Value *foldAndOrOfICmpsOfAndWithPow2(ICmpInst *LHS, ICmpInst *RHS, bool JoinedByAnd, Instruction &CxtI); + Value *matchSelectFromAndOr(Value *A, Value *B, Value *C, Value *D); + Value *getSelectCondition(Value *A, Value *B); + public: /// Inserts an instruction \p New before instruction \p Old /// diff --git a/llvm/test/Transforms/InstCombine/logical-select.ll b/llvm/test/Transforms/InstCombine/logical-select.ll index 3ee0ba169b3..dc4c04b6991 100644 --- a/llvm/test/Transforms/InstCombine/logical-select.ll +++ b/llvm/test/Transforms/InstCombine/logical-select.ll @@ -535,12 +535,9 @@ define <4 x i32> @vec_sel_xor_multi_use(<4 x i32> %a, <4 x i32> %b, <4 x i1> %c) define i32 @allSignBits(i32 %cond, i32 %tval, i32 %fval) { ; CHECK-LABEL: @allSignBits( -; CHECK-NEXT: [[BITMASK:%.*]] = ashr i32 [[COND:%.*]], 31 -; CHECK-NEXT: [[NOT_BITMASK:%.*]] = xor i32 [[BITMASK]], -1 -; CHECK-NEXT: [[A1:%.*]] = and i32 [[BITMASK]], [[TVAL:%.*]] -; CHECK-NEXT: [[A2:%.*]] = and i32 [[NOT_BITMASK]], [[FVAL:%.*]] -; CHECK-NEXT: [[SEL:%.*]] = or i32 [[A1]], [[A2]] -; CHECK-NEXT: ret i32 [[SEL]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[COND:%.*]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TVAL:%.*]], i32 [[FVAL:%.*]] +; CHECK-NEXT: ret i32 [[TMP2]] ; %bitmask = ashr i32 %cond, 31 %not_bitmask = xor i32 %bitmask, -1 @@ -552,12 +549,9 @@ define i32 @allSignBits(i32 %cond, i32 %tval, i32 %fval) { define <4 x i8> @allSignBits_vec(<4 x i8> %cond, <4 x i8> %tval, <4 x i8> %fval) { ; CHECK-LABEL: @allSignBits_vec( -; CHECK-NEXT: [[BITMASK:%.*]] = ashr <4 x i8> [[COND:%.*]], <i8 7, i8 7, i8 7, i8 7> -; CHECK-NEXT: [[NOT_BITMASK:%.*]] = xor <4 x i8> [[BITMASK]], <i8 -1, i8 -1, i8 -1, i8 -1> -; CHECK-NEXT: [[A1:%.*]] = and <4 x i8> [[BITMASK]], [[TVAL:%.*]] -; CHECK-NEXT: [[A2:%.*]] = and <4 x i8> [[NOT_BITMASK]], [[FVAL:%.*]] -; CHECK-NEXT: [[SEL:%.*]] = or <4 x i8> [[A2]], [[A1]] -; CHECK-NEXT: ret <4 x i8> [[SEL]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i8> [[COND:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1> +; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i8> [[FVAL:%.*]], <4 x i8> [[TVAL:%.*]] +; CHECK-NEXT: ret <4 x i8> [[TMP2]] ; %bitmask = ashr <4 x i8> %cond, <i8 7, i8 7, i8 7, i8 7> %not_bitmask = xor <4 x i8> %bitmask, <i8 -1, i8 -1, i8 -1, i8 -1> @@ -567,3 +561,26 @@ define <4 x i8> @allSignBits_vec(<4 x i8> %cond, <4 x i8> %tval, <4 x i8> %fval) ret <4 x i8> %sel } +; Negative test - make sure that bitcasts from FP do not cause a crash. + +define <2 x i64> @fp_bitcast(<4 x i1> %cmp, <2 x double> %a, <2 x double> %b) { +; CHECK-LABEL: @fp_bitcast( +; CHECK-NEXT: [[SIA:%.*]] = fptosi <2 x double> [[A:%.*]] to <2 x i64> +; CHECK-NEXT: [[SIB:%.*]] = fptosi <2 x double> [[B:%.*]] to <2 x i64> +; CHECK-NEXT: [[BC1:%.*]] = bitcast <2 x double> [[A]] to <2 x i64> +; CHECK-NEXT: [[AND1:%.*]] = and <2 x i64> [[SIA]], [[BC1]] +; CHECK-NEXT: [[BC2:%.*]] = bitcast <2 x double> [[B]] to <2 x i64> +; CHECK-NEXT: [[AND2:%.*]] = and <2 x i64> [[SIB]], [[BC2]] +; CHECK-NEXT: [[OR:%.*]] = or <2 x i64> [[AND2]], [[AND1]] +; CHECK-NEXT: ret <2 x i64> [[OR]] +; + %sia = fptosi <2 x double> %a to <2 x i64> + %sib = fptosi <2 x double> %b to <2 x i64> + %bc1 = bitcast <2 x double> %a to <2 x i64> + %and1 = and <2 x i64> %sia, %bc1 + %bc2 = bitcast <2 x double> %b to <2 x i64> + %and2 = and <2 x i64> %sib, %bc2 + %or = or <2 x i64> %and2, %and1 + ret <2 x i64> %or +} + diff --git a/llvm/test/Transforms/InstCombine/vec_sext.ll b/llvm/test/Transforms/InstCombine/vec_sext.ll index f244d49527b..39bd4087416 100644 --- a/llvm/test/Transforms/InstCombine/vec_sext.ll +++ b/llvm/test/Transforms/InstCombine/vec_sext.ll @@ -4,12 +4,9 @@ define <4 x i32> @vec_select(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: @vec_select( ; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]] -; CHECK-NEXT: [[B_LOBIT1:%.*]] = ashr <4 x i32> [[B:%.*]], <i32 31, i32 31, i32 31, i32 31> -; CHECK-NEXT: [[T1:%.*]] = xor <4 x i32> [[B_LOBIT1]], <i32 -1, i32 -1, i32 -1, i32 -1> -; CHECK-NEXT: [[T2:%.*]] = and <4 x i32> [[T1]], [[A]] -; CHECK-NEXT: [[T3:%.*]] = and <4 x i32> [[B_LOBIT1]], [[SUB]] -; CHECK-NEXT: [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]] -; CHECK-NEXT: ret <4 x i32> [[COND]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1> +; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[A]], <4 x i32> [[SUB]] +; CHECK-NEXT: ret <4 x i32> [[TMP2]] ; %cmp = icmp slt <4 x i32> %b, zeroinitializer %sext = sext <4 x i1> %cmp to <4 x i32> @@ -26,12 +23,9 @@ define <4 x i32> @vec_select(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @vec_select_alternate_sign_bit_test(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: @vec_select_alternate_sign_bit_test( ; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]] -; CHECK-NEXT: [[B_LOBIT1:%.*]] = ashr <4 x i32> [[B:%.*]], <i32 31, i32 31, i32 31, i32 31> -; CHECK-NEXT: [[B_LOBIT1_NOT:%.*]] = xor <4 x i32> [[B_LOBIT1]], <i32 -1, i32 -1, i32 -1, i32 -1> -; CHECK-NEXT: [[T2:%.*]] = and <4 x i32> [[B_LOBIT1]], [[A]] -; CHECK-NEXT: [[T3:%.*]] = and <4 x i32> [[B_LOBIT1_NOT]], [[SUB]] -; CHECK-NEXT: [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]] -; CHECK-NEXT: ret <4 x i32> [[COND]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1> +; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[SUB]], <4 x i32> [[A]] +; CHECK-NEXT: ret <4 x i32> [[TMP2]] ; %cmp = icmp sgt <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1> %sext = sext <4 x i1> %cmp to <4 x i32> |
