diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedPredExynos.td | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td b/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td index f8533d18022..967245bcba4 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td +++ b/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td @@ -88,12 +88,19 @@ def ExynosResetFn : TIIPredicate< [ADR, ADRP, MOVNWi, MOVNXi, MOVZWi, MOVZXi], - MCReturnStatement<TruePred>>], + MCReturnStatement<TruePred>>, + MCOpcodeSwitchCase< + [ORRWri, ORRXri], + MCReturnStatement< + CheckAll< + [CheckIsRegOperand<1>, + CheckAny< + [CheckRegOperand<1, WZR>, + CheckRegOperand<1, XZR>]>]>>>], MCReturnStatement< CheckAny< [IsCopyIdiomFn, - IsZeroFPIdiomFn, - IsZeroIdiomFn]>>>>; + IsZeroFPIdiomFn]>>>>; def ExynosResetPred : MCSchedPredicate<ExynosResetFn>; // Identify EXTR as the alias for ROR (immediate). |
