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-rw-r--r--lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp26
-rw-r--r--lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp20
-rw-r--r--llvm/include/llvm/MC/MCAsmInfo.h16
-rw-r--r--llvm/include/llvm/MC/MCInstrInfo.h4
-rw-r--r--llvm/lib/CodeGen/MachineBasicBlock.cpp2
-rw-r--r--llvm/lib/CodeGen/TargetInstrInfo.cpp4
-rw-r--r--llvm/lib/MC/MCDisassembler/Disassembler.cpp2
-rw-r--r--llvm/lib/MC/MCParser/AsmLexer.cpp6
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp4
-rw-r--r--llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp2
-rw-r--r--llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h2
-rw-r--r--llvm/lib/Target/Mips/Mips16InstrInfo.cpp4
-rw-r--r--llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp2
-rw-r--r--llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp12
-rw-r--r--llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h2
-rw-r--r--llvm/tools/llvm-objdump/MachODump.cpp2
16 files changed, 55 insertions, 55 deletions
diff --git a/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp b/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
index 21f57dbf7a8..8cc34c171c7 100644
--- a/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
+++ b/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
@@ -1101,7 +1101,7 @@ bool EmulateInstructionMIPS::EvaluateInstruction(uint32_t evaluate_options) {
* mc_insn.getOpcode() returns decoded opcode. However to make use
* of llvm::Mips::<insn> we would need "MipsGenInstrInfo.inc".
*/
- const char *op_name = m_insn_info->getName(mc_insn.getOpcode());
+ const char *op_name = m_insn_info->getName(mc_insn.getOpcode()).data();
if (op_name == NULL)
return false;
@@ -1373,7 +1373,7 @@ bool EmulateInstructionMIPS::Emulate_SUBU_ADDU(llvm::MCInst &insn) {
bool success = false;
uint64_t result;
uint8_t src, dst, rt;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
@@ -1834,7 +1834,7 @@ bool EmulateInstructionMIPS::Emulate_BXX_3ops(llvm::MCInst &insn) {
bool success = false;
uint32_t rs, rt;
int32_t offset, pc, target = 0, rs_val, rt_val;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
@@ -1886,7 +1886,7 @@ bool EmulateInstructionMIPS::Emulate_BXX_3ops_C(llvm::MCInst &insn) {
bool success = false;
uint32_t rs, rt;
int32_t offset, pc, target = 0, rs_val, rt_val;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
@@ -1969,7 +1969,7 @@ bool EmulateInstructionMIPS::Emulate_Bcond_Link_C(llvm::MCInst &insn) {
uint32_t rs;
int32_t offset, pc, target = 0;
int32_t rs_val;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
@@ -2038,7 +2038,7 @@ bool EmulateInstructionMIPS::Emulate_Bcond_Link(llvm::MCInst &insn) {
uint32_t rs;
int32_t offset, pc, target = 0;
int32_t rs_val;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
@@ -2088,7 +2088,7 @@ bool EmulateInstructionMIPS::Emulate_BXX_2ops(llvm::MCInst &insn) {
uint32_t rs;
int32_t offset, pc, target = 0;
int32_t rs_val;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
@@ -2144,7 +2144,7 @@ bool EmulateInstructionMIPS::Emulate_BXX_2ops_C(llvm::MCInst &insn) {
uint32_t rs;
int32_t offset, pc, target = 0;
int32_t rs_val;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
@@ -2236,7 +2236,7 @@ bool EmulateInstructionMIPS::Emulate_Branch_MM(llvm::MCInst &insn) {
bool success = false;
int32_t target = 0;
uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
bool update_ra = false;
uint32_t ra_offset = 0;
@@ -2336,7 +2336,7 @@ bool EmulateInstructionMIPS::Emulate_Branch_MM(llvm::MCInst &insn) {
bool EmulateInstructionMIPS::Emulate_JALRx16_MM(llvm::MCInst &insn) {
bool success = false;
uint32_t ra_offset = 0;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
uint32_t rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
@@ -2375,7 +2375,7 @@ bool EmulateInstructionMIPS::Emulate_JALRx16_MM(llvm::MCInst &insn) {
bool EmulateInstructionMIPS::Emulate_JALx(llvm::MCInst &insn) {
bool success = false;
uint32_t offset = 0, target = 0, pc = 0, ra_offset = 0;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
/*
* JALS target
@@ -2735,7 +2735,7 @@ bool EmulateInstructionMIPS::Emulate_FP_branch(llvm::MCInst &insn) {
bool success = false;
uint32_t cc, fcsr;
int32_t pc, offset, target = 0;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
cc = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
@@ -2860,7 +2860,7 @@ bool EmulateInstructionMIPS::Emulate_3D_branch(llvm::MCInst &insn) {
bool success = false;
uint32_t cc, fcsr;
int32_t pc, offset, target = 0;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
cc = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
diff --git a/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp b/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
index 1c7d95f39ec..c054760be8a 100644
--- a/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ b/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -953,7 +953,7 @@ bool EmulateInstructionMIPS64::EvaluateInstruction(uint32_t evaluate_options) {
* mc_insn.getOpcode() returns decoded opcode. However to make use
* of llvm::Mips::<insn> we would need "MipsGenInstrInfo.inc".
*/
- const char *op_name = m_insn_info->getName(mc_insn.getOpcode());
+ const char *op_name = m_insn_info->getName(mc_insn.getOpcode()).data();
if (op_name == NULL)
return false;
@@ -1239,7 +1239,7 @@ bool EmulateInstructionMIPS64::Emulate_DSUBU_DADDU(llvm::MCInst &insn) {
bool success = false;
uint64_t result;
uint8_t src, dst, rt;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
@@ -1318,7 +1318,7 @@ bool EmulateInstructionMIPS64::Emulate_BXX_3ops(llvm::MCInst &insn) {
bool success = false;
uint32_t rs, rt;
int64_t offset, pc, rs_val, rt_val, target = 0;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
rt = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
@@ -1371,7 +1371,7 @@ bool EmulateInstructionMIPS64::Emulate_Bcond_Link(llvm::MCInst &insn) {
uint32_t rs;
int64_t offset, pc, target = 0;
int64_t rs_val;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
@@ -1481,7 +1481,7 @@ bool EmulateInstructionMIPS64::Emulate_Bcond_Link_C(llvm::MCInst &insn) {
bool success = false;
uint32_t rs;
int64_t offset, pc, rs_val, target = 0;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
@@ -1549,7 +1549,7 @@ bool EmulateInstructionMIPS64::Emulate_BXX_2ops(llvm::MCInst &insn) {
bool success = false;
uint32_t rs;
int64_t offset, pc, rs_val, target = 0;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
@@ -1636,7 +1636,7 @@ bool EmulateInstructionMIPS64::Emulate_BXX_3ops_C(llvm::MCInst &insn) {
bool success = false;
uint32_t rs, rt;
int64_t offset, pc, rs_val, rt_val, target = 0;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
@@ -1719,7 +1719,7 @@ bool EmulateInstructionMIPS64::Emulate_BXX_2ops_C(llvm::MCInst &insn) {
uint32_t rs;
int64_t offset, pc, target = 0;
int64_t rs_val;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
rs = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
@@ -1970,7 +1970,7 @@ bool EmulateInstructionMIPS64::Emulate_FP_branch(llvm::MCInst &insn) {
bool success = false;
uint32_t cc, fcsr;
int64_t pc, offset, target = 0;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
/*
* BC1F cc, offset
@@ -2104,7 +2104,7 @@ bool EmulateInstructionMIPS64::Emulate_3D_branch(llvm::MCInst &insn) {
bool success = false;
uint32_t cc, fcsr;
int64_t pc, offset, target = 0;
- const char *op_name = m_insn_info->getName(insn.getOpcode());
+ const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
cc = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
offset = insn.getOperand(1).getImm();
diff --git a/llvm/include/llvm/MC/MCAsmInfo.h b/llvm/include/llvm/MC/MCAsmInfo.h
index 4932a17307e..f898bf5288d 100644
--- a/llvm/include/llvm/MC/MCAsmInfo.h
+++ b/llvm/include/llvm/MC/MCAsmInfo.h
@@ -103,7 +103,7 @@ protected:
/// This indicates the comment character used by the assembler. Defaults to
/// "#"
- const char *CommentString;
+ StringRef CommentString;
/// This is appended to emitted labels. Defaults to ":"
const char *LabelSuffix;
@@ -117,17 +117,17 @@ protected:
/// This prefix is used for globals like constant pool entries that are
/// completely private to the .s file and should not have names in the .o
/// file. Defaults to "L"
- const char *PrivateGlobalPrefix;
+ StringRef PrivateGlobalPrefix;
/// This prefix is used for labels for basic blocks. Defaults to the same as
/// PrivateGlobalPrefix.
- const char *PrivateLabelPrefix;
+ StringRef PrivateLabelPrefix;
/// This prefix is used for symbols that should be passed through the
/// assembler but be removed by the linker. This is 'l' on Darwin, currently
/// used for some ObjC metadata. The default of "" meast that for this system
/// a plain private symbol should be used. Defaults to "".
- const char *LinkerPrivateGlobalPrefix;
+ StringRef LinkerPrivateGlobalPrefix;
/// If these are nonempty, they contain a directive to emit before and after
/// an inline assembly statement. Defaults to "#APP\n", "#NO_APP\n"
@@ -468,17 +468,17 @@ public:
/// printed.
unsigned getCommentColumn() const { return 40; }
- const char *getCommentString() const { return CommentString; }
+ StringRef getCommentString() const { return CommentString; }
const char *getLabelSuffix() const { return LabelSuffix; }
bool useAssignmentForEHBegin() const { return UseAssignmentForEHBegin; }
bool needsLocalForSize() const { return NeedsLocalForSize; }
- const char *getPrivateGlobalPrefix() const { return PrivateGlobalPrefix; }
- const char *getPrivateLabelPrefix() const { return PrivateLabelPrefix; }
+ StringRef getPrivateGlobalPrefix() const { return PrivateGlobalPrefix; }
+ StringRef getPrivateLabelPrefix() const { return PrivateLabelPrefix; }
bool hasLinkerPrivateGlobalPrefix() const {
return LinkerPrivateGlobalPrefix[0] != '\0';
}
- const char *getLinkerPrivateGlobalPrefix() const {
+ StringRef getLinkerPrivateGlobalPrefix() const {
if (hasLinkerPrivateGlobalPrefix())
return LinkerPrivateGlobalPrefix;
return getPrivateGlobalPrefix();
diff --git a/llvm/include/llvm/MC/MCInstrInfo.h b/llvm/include/llvm/MC/MCInstrInfo.h
index 70c86587b08..80f1f320b7c 100644
--- a/llvm/include/llvm/MC/MCInstrInfo.h
+++ b/llvm/include/llvm/MC/MCInstrInfo.h
@@ -48,9 +48,9 @@ public:
}
/// \brief Returns the name for the instructions with the given opcode.
- const char *getName(unsigned Opcode) const {
+ StringRef getName(unsigned Opcode) const {
assert(Opcode < NumOpcodes && "Invalid opcode!");
- return &InstrNameData[InstrNameIndices[Opcode]];
+ return StringRef(&InstrNameData[InstrNameIndices[Opcode]]);
}
};
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 55138f64198..57684cdcc2f 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -51,7 +51,7 @@ MCSymbol *MachineBasicBlock::getSymbol() const {
if (!CachedMCSymbol) {
const MachineFunction *MF = getParent();
MCContext &Ctx = MF->getContext();
- const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
+ auto Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
assert(getNumber() >= 0 && "cannot get label for unreachable MBB");
CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
Twine(MF->getFunctionNumber()) +
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index d71f84d1249..7ac2210ac52 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -84,8 +84,8 @@ unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
strlen(MAI.getSeparatorString())) == 0) {
atInsnStart = true;
- } else if (strncmp(Str, MAI.getCommentString(),
- strlen(MAI.getCommentString())) == 0) {
+ } else if (strncmp(Str, MAI.getCommentString().data(),
+ MAI.getCommentString().size()) == 0) {
// Stop counting as an instruction after a comment until the next
// separator.
atInsnStart = false;
diff --git a/llvm/lib/MC/MCDisassembler/Disassembler.cpp b/llvm/lib/MC/MCDisassembler/Disassembler.cpp
index 094ad7cc5eb..aa5072743bd 100644
--- a/llvm/lib/MC/MCDisassembler/Disassembler.cpp
+++ b/llvm/lib/MC/MCDisassembler/Disassembler.cpp
@@ -138,7 +138,7 @@ static void emitComments(LLVMDisasmContext *DC,
StringRef Comments = DC->CommentsToEmit.str();
// Get the default information for printing a comment.
const MCAsmInfo *MAI = DC->getAsmInfo();
- const char *CommentBegin = MAI->getCommentString();
+ StringRef CommentBegin = MAI->getCommentString();
unsigned CommentColumn = MAI->getCommentColumn();
bool IsFirst = true;
while (!Comments.empty()) {
diff --git a/llvm/lib/MC/MCParser/AsmLexer.cpp b/llvm/lib/MC/MCParser/AsmLexer.cpp
index d0c8bce0382..0fa7fbdc7b6 100644
--- a/llvm/lib/MC/MCParser/AsmLexer.cpp
+++ b/llvm/lib/MC/MCParser/AsmLexer.cpp
@@ -511,16 +511,16 @@ size_t AsmLexer::peekTokens(MutableArrayRef<AsmToken> Buf,
}
bool AsmLexer::isAtStartOfComment(const char *Ptr) {
- const char *CommentString = MAI.getCommentString();
+ StringRef CommentString = MAI.getCommentString();
- if (CommentString[1] == '\0')
+ if (CommentString.size() == 1)
return CommentString[0] == Ptr[0];
// Allow # preprocessor commments also be counted as comments for "##" cases
if (CommentString[1] == '#')
return CommentString[0] == Ptr[0];
- return strncmp(Ptr, CommentString, strlen(CommentString)) == 0;
+ return strncmp(Ptr, CommentString.data(), CommentString.size()) == 0;
}
bool AsmLexer::isAtStatementSeparator(const char *Ptr) {
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 7681683540b..9704bd7cfc2 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1541,8 +1541,8 @@ unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
Length += MAI.getMaxInstLength();
atInsnStart = false;
}
- if (atInsnStart && strncmp(Str, MAI.getCommentString(),
- strlen(MAI.getCommentString())) == 0)
+ if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
+ MAI.getCommentString().size()) == 0)
atInsnStart = false;
}
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
index 941cbd6dc35..eaae432f6da 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
@@ -306,7 +306,7 @@ int HexagonMCInstrInfo::getMinValue(MCInstrInfo const &MCII,
return 0;
}
-char const *HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
+StringRef HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
MCInst const &MCI) {
return MCII.getName(MCI.getOpcode());
}
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
index 58a8f68b984..cd521c16001 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
@@ -133,7 +133,7 @@ int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI);
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI);
// Return instruction name
-char const *getName(MCInstrInfo const &MCII, MCInst const &MCI);
+StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI);
// Return the operand index for the new value.
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI);
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
index c8baeef344a..35ef31749f4 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -510,8 +510,8 @@ unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str,
Length += MAI.getMaxInstLength();
atInsnStart = false;
}
- if (atInsnStart && strncmp(Str, MAI.getCommentString(),
- strlen(MAI.getCommentString())) == 0)
+ if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
+ MAI.getCommentString().size()) == 0)
atInsnStart = false;
}
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index 008dead5d0a..c9b53e6dda7 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -96,7 +96,7 @@ void llvm::X86Disassembler::Debug(const char *file, unsigned line,
dbgs() << file << ":" << line << ": " << s;
}
-const char *llvm::X86Disassembler::GetInstrName(unsigned Opcode,
+StringRef llvm::X86Disassembler::GetInstrName(unsigned Opcode,
const void *mii) {
const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
return MII->getName(Opcode);
diff --git a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
index b0a150ab564..ab64d6fcf70 100644
--- a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
@@ -825,7 +825,7 @@ static int getIDWithAttrMask(uint16_t* instructionID,
* @param orig - The instruction that is not 16-bit
* @param equiv - The instruction that is 16-bit
*/
-static bool is16BitEquivalent(const char* orig, const char* equiv) {
+static bool is16BitEquivalent(const char *orig, const char *equiv) {
off_t i;
for (i = 0;; i++) {
@@ -850,7 +850,7 @@ static bool is16BitEquivalent(const char* orig, const char* equiv) {
*
* @param name - The instruction that is not 16-bit
*/
-static bool is64Bit(const char* name) {
+static bool is64Bit(const char *name) {
off_t i;
for (i = 0;; ++i) {
@@ -1044,9 +1044,9 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
return 0;
}
- const char *SpecName = GetInstrName(instructionIDWithREXW, miiArg);
+ auto SpecName = GetInstrName(instructionIDWithREXW, miiArg);
// If not a 64-bit instruction. Switch the opcode.
- if (!is64Bit(SpecName)) {
+ if (!is64Bit(SpecName.data())) {
insn->instructionID = instructionIDWithREXW;
insn->spec = specifierForUID(instructionIDWithREXW);
return 0;
@@ -1092,7 +1092,7 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
const struct InstructionSpecifier *spec;
uint16_t instructionIDWithOpsize;
- const char *specName, *specWithOpSizeName;
+ llvm::StringRef specName, specWithOpSizeName;
spec = specifierForUID(instructionID);
@@ -1112,7 +1112,7 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
specName = GetInstrName(instructionID, miiArg);
specWithOpSizeName = GetInstrName(instructionIDWithOpsize, miiArg);
- if (is16BitEquivalent(specName, specWithOpSizeName) &&
+ if (is16BitEquivalent(specName.data(), specWithOpSizeName.data()) &&
(insn->mode == MODE_16BIT) ^ insn->prefixPresent[0x66]) {
insn->instructionID = instructionIDWithOpsize;
insn->spec = specifierForUID(instructionIDWithOpsize);
diff --git a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
index 24d24a265b4..b07fd0b17d3 100644
--- a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
+++ b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
@@ -674,7 +674,7 @@ int decodeInstruction(InternalInstruction *insn,
/// \param s The message to print.
void Debug(const char *file, unsigned line, const char *s);
-const char *GetInstrName(unsigned Opcode, const void *mii);
+StringRef GetInstrName(unsigned Opcode, const void *mii);
} // namespace X86Disassembler
} // namespace llvm
diff --git a/llvm/tools/llvm-objdump/MachODump.cpp b/llvm/tools/llvm-objdump/MachODump.cpp
index 804a93967f5..a2f0e8dc312 100644
--- a/llvm/tools/llvm-objdump/MachODump.cpp
+++ b/llvm/tools/llvm-objdump/MachODump.cpp
@@ -6397,7 +6397,7 @@ static void emitComments(raw_svector_ostream &CommentStream,
// Flush the stream before taking its content.
StringRef Comments = CommentsToEmit.str();
// Get the default information for printing a comment.
- const char *CommentBegin = MAI.getCommentString();
+ StringRef CommentBegin = MAI.getCommentString();
unsigned CommentColumn = MAI.getCommentColumn();
bool IsFirst = true;
while (!Comments.empty()) {
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