diff options
22 files changed, 37 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index 79b1a7fddba..beed8e0e52d 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -117,6 +117,8 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT, initAsmInfo(); } +AArch64TargetMachine::~AArch64TargetMachine() {} + const AArch64Subtarget * AArch64TargetMachine::getSubtargetImpl(const Function &F) const { AttributeSet FnAttrs = F.getAttributes(); diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h index c9939992115..75c65c57905 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h @@ -33,6 +33,8 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool IsLittleEndian); + ~AArch64TargetMachine() override; + const AArch64Subtarget *getSubtargetImpl() const override { return &Subtarget; } diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 5164a03d5fc..88d6c5e7fb9 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -69,6 +69,8 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft; } +ARMBaseTargetMachine::~ARMBaseTargetMachine() {} + const ARMSubtarget * ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const { AttributeSet FnAttrs = F.getAttributes(); diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h index 2842bc888c6..fba0ec22c17 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.h +++ b/llvm/lib/Target/ARM/ARMTargetMachine.h @@ -35,6 +35,7 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle); + ~ARMBaseTargetMachine() override; const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; } const ARMSubtarget *getSubtargetImpl(const Function &F) const override; diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 9a35e1f8b75..cd18dfb6305 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -75,6 +75,8 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, initAsmInfo(); } +HexagonTargetMachine::~HexagonTargetMachine() {} + namespace { /// Hexagon Code Generator Pass Configuration Options. class HexagonPassConfig : public TargetPassConfig { diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h index 9f3a20e6006..4a9f44732a6 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h @@ -31,6 +31,7 @@ public: StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + ~HexagonTargetMachine() override; const HexagonSubtarget *getSubtargetImpl() const override { return &Subtarget; diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp index ef758183217..8cee01677bf 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -36,6 +36,8 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, StringRef TT, initAsmInfo(); } +MSP430TargetMachine::~MSP430TargetMachine() {} + namespace { /// MSP430 Code Generator Pass Configuration Options. class MSP430PassConfig : public TargetPassConfig { diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.h b/llvm/lib/Target/MSP430/MSP430TargetMachine.h index abe064382b6..0e54ed631be 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.h +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.h @@ -32,6 +32,7 @@ public: StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + ~MSP430TargetMachine() override; const MSP430Subtarget *getSubtargetImpl() const override { return &Subtarget; diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 107fef56796..33280e37a40 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -69,6 +69,8 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT, initAsmInfo(); } +MipsTargetMachine::~MipsTargetMachine() {} + void MipsebTargetMachine::anchor() { } MipsebTargetMachine:: diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h index 2b64600bca5..1349f82c3e0 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.h +++ b/llvm/lib/Target/Mips/MipsTargetMachine.h @@ -38,6 +38,7 @@ public: MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle); + ~MipsTargetMachine() override; void addAnalysisPasses(PassManagerBase &PM) override; diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp index ef12c4974e3..d87693f892d 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -80,6 +80,8 @@ NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT, initAsmInfo(); } +NVPTXTargetMachine::~NVPTXTargetMachine() {} + void NVPTXTargetMachine32::anchor() {} NVPTXTargetMachine32::NVPTXTargetMachine32( diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h index 4794c2ebef6..a726bd18983 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h @@ -36,6 +36,8 @@ public: const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit); + ~NVPTXTargetMachine() override; + const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; } ManagedStringPool *getManagedStrPool() const { diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 6e4c907e2e2..f15189c6761 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -85,6 +85,8 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, initAsmInfo(); } +PPCTargetMachine::~PPCTargetMachine() {} + void PPC32TargetMachine::anchor() { } PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h index 23718602725..5095d736a65 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h @@ -35,6 +35,8 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + ~PPCTargetMachine() override; + const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; } const PPCSubtarget *getSubtargetImpl(const Function &F) const override; diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index 31cf1c12584..489bb691401 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -38,6 +38,8 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, initAsmInfo(); } +SparcTargetMachine::~SparcTargetMachine() {} + namespace { /// Sparc Code Generator Pass Configuration Options. class SparcPassConfig : public TargetPassConfig { diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h index f73c5c527cf..096e7c8485a 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.h +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h @@ -28,6 +28,7 @@ public: StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit); + ~SparcTargetMachine() override; const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; } diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp index 20332629adf..d7c432e364b 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -31,6 +31,8 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT, initAsmInfo(); } +SystemZTargetMachine::~SystemZTargetMachine() {} + namespace { /// SystemZ Code Generator Pass Configuration Options. class SystemZPassConfig : public TargetPassConfig { diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h index f4dbae2680c..9fae5e43e75 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h @@ -31,6 +31,7 @@ public: StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + ~SystemZTargetMachine() override; // Override TargetMachine. const SystemZSubtarget *getSubtargetImpl() const override { diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index 198ce4277c1..8802febfc03 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -29,8 +29,6 @@ extern "C" void LLVMInitializeX86Target() { RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target); } -void X86TargetMachine::anchor() { } - static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { if (TT.isOSBinFormatMachO()) { if (TT.getArch() == Triple::x86_64) @@ -72,6 +70,8 @@ X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, initAsmInfo(); } +X86TargetMachine::~X86TargetMachine() {} + const X86Subtarget * X86TargetMachine::getSubtargetImpl(const Function &F) const { AttributeSet FnAttrs = F.getAttributes(); diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h index 1d21a0c96e3..916278cd7de 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.h +++ b/llvm/lib/Target/X86/X86TargetMachine.h @@ -23,7 +23,6 @@ namespace llvm { class StringRef; class X86TargetMachine final : public LLVMTargetMachine { - virtual void anchor(); std::unique_ptr<TargetLoweringObjectFile> TLOF; X86Subtarget Subtarget; @@ -34,6 +33,8 @@ public: StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + ~X86TargetMachine() override; + const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; } const X86Subtarget *getSubtargetImpl(const Function &F) const override; diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp index 1252ece9c63..0fa8c219654 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -32,6 +32,8 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, initAsmInfo(); } +XCoreTargetMachine::~XCoreTargetMachine() {} + namespace { /// XCore Code Generator Pass Configuration Options. class XCorePassConfig : public TargetPassConfig { diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.h b/llvm/lib/Target/XCore/XCoreTargetMachine.h index e4c0bbf14d9..8ff9269821d 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.h +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.h @@ -27,6 +27,7 @@ public: StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + ~XCoreTargetMachine() override; const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; } |
