diff options
| -rw-r--r-- | llvm/include/llvm/Target/TargetOptions.h | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFastISel.cpp | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 3 |
3 files changed, 18 insertions, 9 deletions
diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h index 68ca5678369..75cfa8c59cb 100644 --- a/llvm/include/llvm/Target/TargetOptions.h +++ b/llvm/include/llvm/Target/TargetOptions.h @@ -48,10 +48,10 @@ namespace llvm { UseSoftFloat(false), NoZerosInBSS(false), JITExceptionHandling(false), JITEmitDebugInfo(false), JITEmitDebugInfoToDisk(false), GuaranteedTailCallOpt(false), DisableTailCalls(false), - StackAlignmentOverride(0), RealignStack(true), EnableFastISel(false), - PositionIndependentExecutable(false), EnableSegmentedStacks(false), - UseInitArray(false), TrapFuncName(""), FloatABIType(FloatABI::Default), - AllowFPOpFusion(FPOpFusion::Standard) + StackAlignmentOverride(0), RealignStack(true), StrictAlign(false), + EnableFastISel(false), PositionIndependentExecutable(false), + EnableSegmentedStacks(false), UseInitArray(false), TrapFuncName(""), + FloatABIType(FloatABI::Default), AllowFPOpFusion(FPOpFusion::Standard) {} /// PrintMachineCode - This flag is enabled when the -print-machineinstrs @@ -155,6 +155,10 @@ namespace llvm { /// automatically realigned, if needed. unsigned RealignStack : 1; + /// StrictAlign - This flag indicates that all memory accesses must be + /// aligned. (ARM only) + unsigned StrictAlign : 1; + /// SSPBufferSize - The minimum size of buffers that will receive stack /// smashing protection when -fstack-protection is used. unsigned SSPBufferSize; diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 6611862ca07..7527c8496de 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -1028,7 +1028,8 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, RC = &ARM::GPRRegClass; break; case MVT::i16: - if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) + if (Alignment && Alignment < 2 && (!Subtarget->allowsUnalignedMem() || + TM.Options.StrictAlign)) return false; if (isThumb2) { @@ -1043,7 +1044,8 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, RC = &ARM::GPRRegClass; break; case MVT::i32: - if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) + if (Alignment && Alignment < 4 && (!Subtarget->allowsUnalignedMem() || + TM.Options.StrictAlign)) return false; if (isThumb2) { @@ -1152,7 +1154,8 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, } break; case MVT::i16: - if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) + if (Alignment && Alignment < 2 && (!Subtarget->allowsUnalignedMem() || + TM.Options.StrictAlign)) return false; if (isThumb2) { @@ -1166,7 +1169,8 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, } break; case MVT::i32: - if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) + if (Alignment && Alignment < 4 && (!Subtarget->allowsUnalignedMem() || + TM.Options.StrictAlign)) return false; if (isThumb2) { diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 3b9558bc2a2..65cc49e1c33 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -9119,7 +9119,8 @@ bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc, bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus - bool AllowsUnaligned = Subtarget->allowsUnalignedMem(); + bool AllowsUnaligned = Subtarget->allowsUnalignedMem() && + !getTargetMachine().Options.StrictAlign; switch (VT.getSimpleVT().SimpleTy) { default: |
