diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index e0e89670067..1a2fcc4d79d 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -532,12 +532,6 @@ def : InstRW<[WriteALULd], (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)", "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>; -// ANDN. -// r,r. -def : InstRW<[WriteALU], (instregex "ANDN(32|64)rr")>; -// r,m. -def : InstRW<[WriteALULd, ReadAfterLd], (instregex "ANDN(32|64)rm")>; - // Define ALU latency variants def ZnWriteALULat2 : SchedWriteRes<[ZnALU]> { let Latency = 2; |
