diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Hexagon/inst_sxth.ll | 10 |
4 files changed, 20 insertions, 8 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index dc58c426e94..e527ab1163c 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -934,7 +934,7 @@ SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) { if (N000 == N2 && N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 && N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) { - SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl, + SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl, MVT::i32, N000); SDNode *Result = CurDAG->getMachineNode(Hexagon::MAXw_rr, dl, MVT::i32, @@ -958,7 +958,7 @@ SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) { if (N000 == N2 && N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 && N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) { - SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl, + SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl, MVT::i32, N000); SDNode *Result = CurDAG->getMachineNode(Hexagon::MINw_rr, dl, MVT::i32, diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 3c7d63487cb..29502eea267 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -716,7 +716,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { case Hexagon::ASLH: case Hexagon::ASRH: case Hexagon::A2_sxtb: - case Hexagon::SXTH: + case Hexagon::A2_sxth: case Hexagon::ZXTB: case Hexagon::ZXTH: return Subtarget.hasV4TOps(); @@ -1315,6 +1315,10 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { case Hexagon::A2_pxorfnew: case Hexagon::A2_pxort: case Hexagon::A2_pxortnew: + case Hexagon::A4_psxthf: + case Hexagon::A4_psxthfnew: + case Hexagon::A4_psxtht: + case Hexagon::A4_psxthtnew: case Hexagon::A4_psxtbf: case Hexagon::A4_psxtbfnew: case Hexagon::A4_psxtbt: @@ -1328,8 +1332,6 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { case Hexagon::ASLH_cNotPt_V4: case Hexagon::ASRH_cPt_V4: case Hexagon::ASRH_cNotPt_V4: - case Hexagon::SXTH_cPt_V4: - case Hexagon::SXTH_cNotPt_V4: case Hexagon::ZXTB_cPt_V4: case Hexagon::ZXTB_cNotPt_V4: case Hexagon::ZXTH_cPt_V4: diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 0e6e69f088b..99db1801052 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -266,6 +266,7 @@ multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> { } defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel; +defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel; // Combines the two integer registers SRC1 and SRC2 into a double register. let isPredicable = 1 in @@ -597,7 +598,6 @@ multiclass ALU32_2op_base2<string mnemonic> { defm ASLH : ALU32_2op_base2<"aslh">, PredNewRel; defm ASRH : ALU32_2op_base2<"asrh">, PredNewRel; -defm SXTH : ALU32_2op_base2<"sxth">, PredNewRel; defm ZXTB : ALU32_2op_base2<"zxtb">, PredNewRel; defm ZXTH : ALU32_2op_base2<"zxth">, PredNewRel; @@ -611,7 +611,7 @@ def : Pat <(sext_inreg (i32 IntRegs:$src1), i8), (A2_sxtb IntRegs:$src1)>; def : Pat <(sext_inreg (i32 IntRegs:$src1), i16), - (SXTH IntRegs:$src1)>; + (A2_sxth IntRegs:$src1)>; //===----------------------------------------------------------------------===// // ALU32/PERM - @@ -2350,7 +2350,7 @@ def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)), // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)). def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)), - (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), + (i64 (SXTW (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))))>; // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)). diff --git a/llvm/test/MC/Hexagon/inst_sxth.ll b/llvm/test/MC/Hexagon/inst_sxth.ll new file mode 100644 index 00000000000..ad0c13b33bb --- /dev/null +++ b/llvm/test/MC/Hexagon/inst_sxth.ll @@ -0,0 +1,10 @@ +;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \ +;; RUN: | llvm-objdump -s - | FileCheck %s + +define i32 @foo (i16 %a) +{ + %1 = sext i16 %a to i32 + ret i32 %1 +} + +; CHECK: 0000 0040e070 00c09f52
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