diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir | 15 |
2 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp index 958b8019c72..9528aee4c50 100644 --- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -952,6 +952,7 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) { unsigned SDSTName; switch (MI->getOpcode()) { case AMDGPU::V_READLANE_B32: + case AMDGPU::V_READLANE_B32_gfx10: case AMDGPU::V_READFIRSTLANE_B32: SDSTName = AMDGPU::OpName::vdst; break; diff --git a/llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir b/llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir index 0796754ddf9..531cca11e47 100644 --- a/llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir +++ b/llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir @@ -304,6 +304,21 @@ body: | S_ENDPGM 0 ... +# Workaround since spilling/restoring SGPRs use real opcodes. +# GCN-LABEL: name: hazard_smem_war_readlane_gfx10 +# GCN: S_LOAD_DWORD_IMM +# GCN: $sgpr_null = S_MOV_B32 0 +# GCN-NEXT: V_READLANE_B32_gfx10 +--- +name: hazard_smem_war_readlane_gfx10 +body: | + bb.0: + liveins: $sgpr0, $sgpr1, $sgpr3, $vgpr0 + $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0 + $sgpr0 = V_READLANE_B32_gfx10 $vgpr0, $sgpr3 + S_ENDPGM 0 +... + # GCN-LABEL: name: hazard_smem_war_readfirstlane # GCN: S_LOAD_DWORD_IMM # GCN: $sgpr_null = S_MOV_B32 0 |
