diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/movmsk.ll | 16 |
2 files changed, 18 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index ee329dc671e..9ced1ac2439 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1792,7 +1792,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, case ISD::BITCAST: // If this is an FP->Int bitcast and if the sign bit is the only // thing demanded, turn this into a FGETSIGN. - if (!Op.getValueType().isVector() && + if (!TLO.LegalOperations() && + !Op.getValueType().isVector() && !Op.getOperand(0).getValueType().isVector() && NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && Op.getOperand(0).getValueType().isFloatingPoint()) { diff --git a/llvm/test/CodeGen/X86/movmsk.ll b/llvm/test/CodeGen/X86/movmsk.ll index 2368548bfa8..928ad037c1c 100644 --- a/llvm/test/CodeGen/X86/movmsk.ll +++ b/llvm/test/CodeGen/X86/movmsk.ll @@ -78,6 +78,22 @@ entry: ret i32 %shr.i } +; PR11570 +define void @float_call_signbit(double %n) { +entry: +; FIXME: This should also use movmskps; we don't form the FGETSIGN node +; in this case, though. +; CHECK: float_call_signbit: +; CHECK: movd %xmm0, %rdi +; FIXME + %t0 = bitcast double %n to i64 + %tobool.i.i.i.i = icmp slt i64 %t0, 0 + tail call void @float_call_signbit_callee(i1 zeroext %tobool.i.i.i.i) + ret void +} +declare void @float_call_signbit_callee(i1 zeroext) + + ; rdar://10247336 ; movmskp{s|d} only set low 4/2 bits, high bits are known zero |
