diff options
40 files changed, 114 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/2r.ll b/llvm/test/CodeGen/Mips/msa/2r.ll index b0061ae0811..7719b7cc0cf 100644 --- a/llvm/test/CodeGen/Mips/msa/2r.ll +++ b/llvm/test/CodeGen/Mips/msa/2r.ll @@ -1,3 +1,5 @@ +; Test the MSA intrinsics that are encoded with the 2R instruction format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll index 9d0765a2523..e03c9a3464f 100644 --- a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll +++ b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 2R instruction format and +; convert scalars to vectors. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_fill_b_ARG1 = global i32 23, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf.ll b/llvm/test/CodeGen/Mips/msa/2rf.ll index 6283cdf7294..74372871ae1 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf.ll @@ -1,3 +1,5 @@ +; Test the MSA intrinsics that are encoded with the 2RF instruction format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_flog2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_exup.ll b/llvm/test/CodeGen/Mips/msa/2rf_exup.ll index 54e416de7da..ca47c95b8a2 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_exup.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_exup.ll @@ -1,3 +1,6 @@ +; Test the MSA floating point conversion intrinsics (e.g. float->double) that +; are encoded with the 2RF instruction format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_fexupl_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll index 4b2ef22434c..c76064a8bad 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll @@ -1,3 +1,6 @@ +; Test the MSA integer to floating point conversion intrinsics that are encoded +; with the 2RF instruction format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_fq.ll b/llvm/test/CodeGen/Mips/msa/2rf_fq.ll index e0f80c09f18..6808a2a99da 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_fq.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_fq.ll @@ -1,3 +1,6 @@ +; Test the MSA fixed-point to floating point conversion intrinsics that are +; encoded with the 2RF instruction format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll index ef5c0c3db12..b5eaad27e90 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll @@ -1,3 +1,7 @@ +; Test the MSA floating point to integer intrinsics that are encoded with the +; 2RF instruction format. This includes conversions but other instructions such +; as fclass are also here. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_tq.ll b/llvm/test/CodeGen/Mips/msa/2rf_tq.ll index 190f93ce6ec..aa7fc8636f4 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_tq.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_tq.ll @@ -1,3 +1,6 @@ +; Test the MSA floating-point to fixed-point conversion intrinsics that are +; encoded with the 2RF instruction format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-a.ll b/llvm/test/CodeGen/Mips/msa/3r-a.ll index 3cdeae4af3a..79b82374a9c 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-a.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-a.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3R instruction format. +; There are lots of these so this covers those beginning with 'a' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_add_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-b.ll b/llvm/test/CodeGen/Mips/msa/3r-b.ll index afcc391e534..786c71f9614 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-b.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-b.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3R instruction format. +; There are lots of these so this covers those beginning with 'b' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-c.ll b/llvm/test/CodeGen/Mips/msa/3r-c.ll index 56636947ac9..0ad6afbe429 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-c.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-c.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3R instruction format. +; There are lots of these so this covers those beginning with 'c' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_ceq_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-d.ll b/llvm/test/CodeGen/Mips/msa/3r-d.ll index 3b20743a5da..ee94e5650d8 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-d.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-d.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3R instruction format. +; There are lots of these so this covers those beginning with 'd' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-i.ll b/llvm/test/CodeGen/Mips/msa/3r-i.ll index b5c6a305d65..2f9acd1f1ed 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-i.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-i.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3R instruction format. +; There are lots of these so this covers those beginning with 'i' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_ilvev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-m.ll b/llvm/test/CodeGen/Mips/msa/3r-m.ll index 7f0cb363d92..041d603dd4d 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-m.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-m.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3R instruction format. +; There are lots of these so this covers those beginning with 'm' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_max_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-p.ll b/llvm/test/CodeGen/Mips/msa/3r-p.ll index 1386533296b..f328cad614d 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-p.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-p.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3R instruction format. +; There are lots of these so this covers those beginning with 'p' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_pckev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-s.ll b/llvm/test/CodeGen/Mips/msa/3r-s.ll index 6c977c636d3..bcc6ba7829c 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-s.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-s.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3R instruction format. +; There are lots of these so this covers those beginning with 's' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-v.ll b/llvm/test/CodeGen/Mips/msa/3r-v.ll index 5c2ab9b2280..055491d6a7f 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-v.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-v.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3R instruction format. +; There are lots of these so this covers those beginning with 'v' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_vshf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_4r.ll b/llvm/test/CodeGen/Mips/msa/3r_4r.ll index c7d189e926d..52f3cd3b880 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_4r.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_4r.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3R instruction format and +; use the result as a third operand. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_maddv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll b/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll index 891d11a2f4e..63592b4b052 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll @@ -1,3 +1,7 @@ +; Test the MSA intrinsics that are encoded with the 3R instruction format and +; use the result as a third operand and results in wider elements than the +; operands had. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_dpadd_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_splat.ll b/llvm/test/CodeGen/Mips/msa/3r_splat.ll index dad61eb8b61..001f723f7d4 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_splat.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_splat.ll @@ -1,3 +1,6 @@ +; Test the MSA splat intrinsics that are encoded with the 3R instruction +; format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_splat_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf.ll b/llvm/test/CodeGen/Mips/msa/3rf.ll index e2d5a208c08..265c8fb4b07 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf.ll @@ -1,3 +1,5 @@ +; Test the MSA intrinsics that are encoded with the 3RF instruction format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll b/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll index cef38fd6e9a..913fe70c06e 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3RF instruction format and +; use the result as a third operand. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_fmadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll b/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll index b490e180385..4fbc69d3c4d 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3RF instruction format and +; use the result as a third operand and perform fixed-point operations. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll b/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll index 45a80116e00..d5713cb9aea 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll @@ -1,3 +1,6 @@ +; Test the MSA floating-point conversion intrinsics that are encoded with the +; 3RF instruction format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll index 6b9998d4b12..6fd46f5e7f2 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3RF instruction format and +; take an integer as an operand. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_fexp2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll index 112f1177b90..3d10ad3ca70 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the 3RF instruction format and +; produce an integer as a result. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_fceq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_q.ll b/llvm/test/CodeGen/Mips/msa/3rf_q.ll index 748fd9c6869..857ae3f617d 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_q.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_q.ll @@ -1,3 +1,6 @@ +; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction +; format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/bit.ll b/llvm/test/CodeGen/Mips/msa/bit.ll index fe36ed7a0a3..28bf0e75bc0 100644 --- a/llvm/test/CodeGen/Mips/msa/bit.ll +++ b/llvm/test/CodeGen/Mips/msa/bit.ll @@ -1,3 +1,5 @@ +; Test the MSA intrinsics that are encoded with the BIT instruction format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_sat_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/bitcast.ll b/llvm/test/CodeGen/Mips/msa/bitcast.ll index fccdbf6df21..03195a84592 100644 --- a/llvm/test/CodeGen/Mips/msa/bitcast.ll +++ b/llvm/test/CodeGen/Mips/msa/bitcast.ll @@ -1,3 +1,5 @@ +; Test the bitcast operation for big-endian and little-endian. + ; RUN: llc -march=mipsel -mattr=+msa < %s | FileCheck -check-prefix=LITENDIAN %s ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=BIGENDIAN %s diff --git a/llvm/test/CodeGen/Mips/msa/elm_copy.ll b/llvm/test/CodeGen/Mips/msa/elm_copy.ll index f31bb506db2..a966043b5de 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_copy.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_copy.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the ELM instruction format and +; are element extraction operations. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_insv.ll b/llvm/test/CodeGen/Mips/msa/elm_insv.ll index be0b5c4f2d3..eb7dbf515d2 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_insv.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_insv.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s -; ; Test the MSA element insertion intrinsics that are encoded with the ELM ; instruction format. +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + @llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_insert_b_ARG3 = global i32 27, align 16 @llvm_mips_insert_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll index 5bddeaf203d..2568ba01f7b 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the ELM instruction format and +; are either shifts or slides. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-a.ll b/llvm/test/CodeGen/Mips/msa/i5-a.ll index fe93534b2ff..f158494f35f 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-a.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-a.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the I5 instruction format. +; There are lots of these so this covers those beginning with 'a' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_addvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-b.ll b/llvm/test/CodeGen/Mips/msa/i5-b.ll index 87d4527124a..165c9a449a6 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-b.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-b.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the I5 instruction format. +; There are lots of these so this covers those beginning with 'b' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-c.ll b/llvm/test/CodeGen/Mips/msa/i5-c.ll index 5e9eed8b2d0..e9ebee40adc 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-c.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-c.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the I5 instruction format. +; There are lots of these so this covers those beginning with 'c' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-m.ll b/llvm/test/CodeGen/Mips/msa/i5-m.ll index 9e358485461..a4677194acb 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-m.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-m.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the I5 instruction format. +; There are lots of these so this covers those beginning with 'm' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_maxi_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-s.ll b/llvm/test/CodeGen/Mips/msa/i5-s.ll index 058e0edba82..616085c7f45 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-s.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-s.ll @@ -1,3 +1,6 @@ +; Test the MSA intrinsics that are encoded with the I5 instruction format. +; There are lots of these so this covers those beginning with 's' + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_subvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i8.ll b/llvm/test/CodeGen/Mips/msa/i8.ll index 5587848158f..e629b046624 100644 --- a/llvm/test/CodeGen/Mips/msa/i8.ll +++ b/llvm/test/CodeGen/Mips/msa/i8.ll @@ -1,3 +1,5 @@ +; Test the MSA intrinsics that are encoded with the I8 instruction format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/spill.ll b/llvm/test/CodeGen/Mips/msa/spill.ll index 33f4a441e27..5c927bfffff 100644 --- a/llvm/test/CodeGen/Mips/msa/spill.ll +++ b/llvm/test/CodeGen/Mips/msa/spill.ll @@ -1,3 +1,6 @@ +; Test that the correct instruction is chosen for spill and reload by trying +; to have 33 live MSA registers simultaneously + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s define i32 @test_i8(<16 x i8>* %p0, <16 x i8>* %q1) nounwind { diff --git a/llvm/test/CodeGen/Mips/msa/vec.ll b/llvm/test/CodeGen/Mips/msa/vec.ll index eb293e8607b..13a23fa2721 100644 --- a/llvm/test/CodeGen/Mips/msa/vec.ll +++ b/llvm/test/CodeGen/Mips/msa/vec.ll @@ -1,7 +1,7 @@ +; Test the MSA intrinsics that are encoded with the VEC instruction format. + ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=ANYENDIAN %s ; RUN: llc -march=mipsel -mattr=+msa < %s | FileCheck -check-prefix=ANYENDIAN %s -; -; Test the MSA intrinsics that are encoded with the VEC instruction format. @llvm_mips_and_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_and_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 |
