diff options
| -rw-r--r-- | llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/atomic_mi.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/commute-two-addr.ll | 2 | ||||
| -rw-r--r-- | llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll | 2 |
4 files changed, 11 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 717b07ca059..1b4fe705eb8 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -1265,6 +1265,13 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi, return true; } + // If we commuted, regB may have changed so we should re-sample it to avoid + // confusing the three address conversion below. + if (Commuted) { + regB = MI.getOperand(SrcIdx).getReg(); + regBKilled = isKilled(MI, regB, MRI, TII, LIS, true); + } + if (MI.isConvertibleTo3Addr()) { // This instruction is potentially convertible to a true // three-address instruction. Check if it is profitable. diff --git a/llvm/test/CodeGen/X86/atomic_mi.ll b/llvm/test/CodeGen/X86/atomic_mi.ll index 631c5fbb89a..7be79113620 100644 --- a/llvm/test/CodeGen/X86/atomic_mi.ll +++ b/llvm/test/CodeGen/X86/atomic_mi.ll @@ -210,8 +210,8 @@ define i32 @add_32r_ret_load(i32* %p, i32 %v) { ; X64-LABEL: add_32r_ret_load: ; X64-NOT: lock ; X64: movl (%rdi), %eax -; X64-NEXT: leal (%rsi,%rax), %ecx -; X64-NEXT: movl %ecx, (%rdi) +; X64-NEXT: addl %eax, %esi +; X64-NEXT: movl %esi, (%rdi) ; X64-NEXT: retq ; X32-LABEL: add_32r_ret_load: ; X32-NOT: lock diff --git a/llvm/test/CodeGen/X86/commute-two-addr.ll b/llvm/test/CodeGen/X86/commute-two-addr.ll index 5b01e2f4e90..656c385e2bc 100644 --- a/llvm/test/CodeGen/X86/commute-two-addr.ll +++ b/llvm/test/CodeGen/X86/commute-two-addr.ll @@ -39,7 +39,7 @@ define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8 entry: ; DARWIN-LABEL: t3: ; DARWIN: shlq $32, %rcx -; DARWIN-NEXT: leaq (%rax,%rcx), %rax +; DARWIN-NEXT: orq %rcx, %rax ; DARWIN-NEXT: shll $8 ; DARWIN-NOT: leaq %tmp21 = zext i32 %lb to i64 diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll index 24be0dc42d6..7925bf01020 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll @@ -23,7 +23,7 @@ ; X32: add ; X32: add ; X32: add -; X32: leal +; X32: add ; X32: %for.body.3 define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp { entry: |
