diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 14 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 91 |
2 files changed, 105 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index 2f9c53f82d4..984efaf3d27 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -317,6 +317,20 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { &ARM::ValueMappings[ARM::SPR3OpsIdx]}); break; } + case G_SITOFP: + case G_UITOFP: { + LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); + LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); + if (FromTy.getSizeInBits() == 32 && + (ToTy.getSizeInBits() == 32 || ToTy.getSizeInBits() == 64)) + OperandsMapping = + ToTy.getSizeInBits() == 64 + ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], + &ARM::ValueMappings[ARM::GPR3OpsIdx]}) + : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx], + &ARM::ValueMappings[ARM::GPR3OpsIdx]}); + break; + } case G_CONSTANT: case G_FRAME_INDEX: case G_GLOBAL_VALUE: diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index 4748eb0db42..8960fa9a7ef 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -73,6 +73,11 @@ define void @test_fptoui_s32() #0 { ret void } define void @test_fptoui_s64() #0 { ret void } + define void @test_sitofp_s32() #0 { ret void } + define void @test_sitofp_s64() #0 { ret void } + define void @test_uitofp_s32() #0 { ret void } + define void @test_uitofp_s64() #0 { ret void } + define void @test_soft_fp_s64() #0 { ret void } attributes #0 = { "target-features"="+vfp2"} @@ -1334,6 +1339,92 @@ body: | BX_RET 14, %noreg, implicit %r0 ... --- +name: test_sitofp_s32 +# CHECK-LABEL: name: test_sitofp_s32 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: gprb, preferred-register: '' } +# CHECK: - { id: 1, class: fprb, preferred-register: '' } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + %1(s32) = G_SITOFP %0 + %s0 = COPY %1(s32) + BX_RET 14, %noreg, implicit %s0 + +... +--- +name: test_sitofp_s64 +# CHECK-LABEL: name: test_sitofp_s64 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: gprb, preferred-register: '' } +# CHECK: - { id: 1, class: fprb, preferred-register: '' } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + %1(s64) = G_SITOFP %0 + %d0 = COPY %1(s64) + BX_RET 14, %noreg, implicit %d0 +... +--- +name: test_uitofp_s32 +# CHECK-LABEL: name: test_uitofp_s32 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: gprb, preferred-register: '' } +# CHECK: - { id: 1, class: fprb, preferred-register: '' } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + %1(s32) = G_UITOFP %0 + %s0 = COPY %1(s32) + BX_RET 14, %noreg, implicit %s0 + +... +--- +name: test_uitofp_s64 +# CHECK-LABEL: name: test_uitofp_s64 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: gprb, preferred-register: '' } +# CHECK: - { id: 1, class: fprb, preferred-register: '' } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + %1(s64) = G_UITOFP %0 + %d0 = COPY %1(s64) + BX_RET 14, %noreg, implicit %d0 +... +--- name: test_soft_fp_s64 # CHECK-LABEL: name: test_soft_fp_s64 legalized: true |
