diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrCompiler.td | 92 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 687 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 50 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86Schedule.td | 88 |
5 files changed, 381 insertions, 540 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 942aa06e740..5751e6c946e 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -8833,8 +8833,8 @@ multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeSt RegisterClass KRC, X86MemOperand memop> { let Predicates = [HasPFI], hasSideEffects = 1 in def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src), - !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"), - [], IIC_SSE_PREFETCH>, EVEX, EVEX_K, Sched<[WriteLoad]>; + !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"), []>, + EVEX, EVEX_K, Sched<[WriteLoad]>; } defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps", diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index 643b1d58e37..3662983965a 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -317,8 +317,7 @@ def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", // that would make it more difficult to rematerialize. let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteMove] in -def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", [], - IIC_MOV>; +def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", []>; // This 64-bit pseudo-move can be used for both a 64-bit constant that is // actually the zero-extension of a 32-bit constant and for labels in the @@ -396,28 +395,28 @@ def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))), let SchedRW = [WriteMicrocoded] in { let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", - [(X86rep_movs i8)], IIC_REP_MOVS>, REP, + [(X86rep_movs i8)]>, REP, Requires<[Not64BitMode]>; def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", - [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16, + [(X86rep_movs i16)]>, REP, OpSize16, Requires<[Not64BitMode]>; def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", - [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32, + [(X86rep_movs i32)]>, REP, OpSize32, Requires<[Not64BitMode]>; } let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", - [(X86rep_movs i8)], IIC_REP_MOVS>, REP, + [(X86rep_movs i8)]>, REP, Requires<[In64BitMode]>; def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", - [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16, + [(X86rep_movs i16)]>, REP, OpSize16, Requires<[In64BitMode]>; def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", - [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32, + [(X86rep_movs i32)]>, REP, OpSize32, Requires<[In64BitMode]>; def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", - [(X86rep_movs i64)], IIC_REP_MOVS>, REP, + [(X86rep_movs i64)]>, REP, Requires<[In64BitMode]>; } @@ -425,36 +424,36 @@ def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", let Defs = [ECX,EDI], isCodeGenOnly = 1 in { let Uses = [AL,ECX,EDI] in def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", - [(X86rep_stos i8)], IIC_REP_STOS>, REP, + [(X86rep_stos i8)]>, REP, Requires<[Not64BitMode]>; let Uses = [AX,ECX,EDI] in def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", - [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16, + [(X86rep_stos i16)]>, REP, OpSize16, Requires<[Not64BitMode]>; let Uses = [EAX,ECX,EDI] in def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", - [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32, + [(X86rep_stos i32)]>, REP, OpSize32, Requires<[Not64BitMode]>; } let Defs = [RCX,RDI], isCodeGenOnly = 1 in { let Uses = [AL,RCX,RDI] in def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", - [(X86rep_stos i8)], IIC_REP_STOS>, REP, - Requires<[In64BitMode]>; + [(X86rep_stos i8)]>, REP, + Requires<[In64BitMode]>; let Uses = [AX,RCX,RDI] in def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", - [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16, - Requires<[In64BitMode]>; + [(X86rep_stos i16)]>, REP, OpSize16, + Requires<[In64BitMode]>; let Uses = [RAX,RCX,RDI] in def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", - [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32, - Requires<[In64BitMode]>; + [(X86rep_stos i32)]>, REP, OpSize32, + Requires<[In64BitMode]>; let Uses = [RAX,RCX,RDI] in def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", - [(X86rep_stos i64)], IIC_REP_STOS>, REP, - Requires<[In64BitMode]>; + [(X86rep_stos i64)]>, REP, + Requires<[In64BitMode]>; } } // SchedRW @@ -759,43 +758,39 @@ defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "X86lock_dec", "dec">; // Atomic compare and swap. multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic, - SDPatternOperator frag, X86MemOperand x86memop, - InstrItinClass itin> { + SDPatternOperator frag, X86MemOperand x86memop> { let isCodeGenOnly = 1, usesCustomInserter = 1 in { def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr), !strconcat(mnemonic, "\t$ptr"), - [(frag addr:$ptr)], itin>, TB, LOCK; + [(frag addr:$ptr)]>, TB, LOCK; } } multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, - string mnemonic, SDPatternOperator frag, - InstrItinClass itin8, InstrItinClass itin> { + string mnemonic, SDPatternOperator frag> { let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in { let Defs = [AL, EFLAGS], Uses = [AL] in def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), - [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK; + [(frag addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; let Defs = [AX, EFLAGS], Uses = [AX] in def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), - [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK; + [(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK; let Defs = [EAX, EFLAGS], Uses = [EAX] in def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), - [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK; + [(frag addr:$ptr, GR32:$swap, 4)]>, TB, OpSize32, LOCK; let Defs = [RAX, EFLAGS], Uses = [RAX] in def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), - [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK; + [(frag addr:$ptr, GR64:$swap, 8)]>, TB, LOCK; } } let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], SchedRW = [WriteALULd, WriteRMW] in { -defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", - X86cas8, i64mem, - IIC_CMPX_LOCK_8B>; +defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", X86cas8, i64mem>; } // This pseudo must be used when the frame uses RBX as @@ -825,16 +820,14 @@ def LCMPXCHG8B_SAVE_EBX : (ins i64mem:$ptr, GR32:$ebx_input, GR32:$ebx_save), !strconcat("cmpxchg8b", "\t$ptr"), [(set GR32:$dst, (X86cas8save_ebx addr:$ptr, GR32:$ebx_input, - GR32:$ebx_save))], - IIC_CMPX_LOCK_8B>; + GR32:$ebx_save))]>; } let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in { defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b", - X86cas16, i128mem, - IIC_CMPX_LOCK_16B>, REX_W; + X86cas16, i128mem>, REX_W; } // Same as LCMPXCHG8B_SAVE_RBX but for the 16 Bytes variant. @@ -847,52 +840,45 @@ def LCMPXCHG16B_SAVE_RBX : (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), !strconcat("cmpxchg16b", "\t$ptr"), [(set GR64:$dst, (X86cas16save_rbx addr:$ptr, GR64:$rbx_input, - GR64:$rbx_save))], - IIC_CMPX_LOCK_16B>; + GR64:$rbx_save))]>; } -defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", - X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>; +defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>; // Atomic exchange and add multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, - string frag, - InstrItinClass itin8, InstrItinClass itin> { + string frag> { let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in { def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr), !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), [(set GR8:$dst, - (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], - itin8>; + (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>; def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr), !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), [(set GR16:$dst, - (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], - itin>, OpSize16; + (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>, + OpSize16; def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr), !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), [(set GR32:$dst, - (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], - itin>, OpSize32; + (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>, + OpSize32; def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val, i64mem:$ptr), !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), [(set GR64:$dst, - (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], - itin>; + (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>; } } -defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add", - IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>, - TB, LOCK; +defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK; /* The following multiclass tries to make sure that in code like * x.store (immediate op x.load(acquire), release) diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index de1e75c6968..1d647798f3b 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -1148,17 +1148,15 @@ let hasSideEffects = 0, SchedRW = [WriteNop] in { // Constructing a stack frame. def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), - "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>; + "enter\t$len, $lvl", []>, Sched<[WriteMicrocoded]>; let SchedRW = [WriteALU] in { let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in -def LEAVE : I<0xC9, RawFrm, - (outs), (ins), "leave", [], IIC_LEAVE>, +def LEAVE : I<0xC9, RawFrm, (outs), (ins), "leave", []>, Requires<[Not64BitMode]>; let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in -def LEAVE64 : I<0xC9, RawFrm, - (outs), (ins), "leave", [], IIC_LEAVE>, +def LEAVE64 : I<0xC9, RawFrm, (outs), (ins), "leave", []>, Requires<[In64BitMode]>; } // SchedRW @@ -1173,50 +1171,50 @@ let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1, let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { let mayLoad = 1, SchedRW = [WriteLoad] in { -def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], - IIC_POP_REG16>, OpSize16; -def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], - IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; -def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], - IIC_POP_REG>, OpSize16; -def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], - IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; +def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, + OpSize16; +def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, + OpSize32, Requires<[Not64BitMode]>; +def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, + OpSize16; +def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, + OpSize32, Requires<[Not64BitMode]>; } // mayLoad, SchedRW let mayStore = 1, mayLoad = 1, SchedRW = [WriteRMW] in { -def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [], - IIC_POP_MEM>, OpSize16; -def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [], - IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>; +def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>, + OpSize16; +def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>, + OpSize32, Requires<[Not64BitMode]>; } // mayStore, mayLoad, WriteRMW let mayStore = 1, SchedRW = [WriteStore] in { -def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[], - IIC_PUSH_REG>, OpSize16; -def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[], - IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; -def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[], - IIC_PUSH_REG>, OpSize16; -def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[], - IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; +def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, + OpSize16; +def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, + OpSize32, Requires<[Not64BitMode]>; +def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, + OpSize16; +def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, + OpSize32, Requires<[Not64BitMode]>; def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), - "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16; + "push{w}\t$imm", []>, OpSize16; def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), - "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16; + "push{w}\t$imm", []>, OpSize16; def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), - "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, + "push{l}\t$imm", []>, OpSize32, Requires<[Not64BitMode]>; def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), - "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, + "push{l}\t$imm", []>, OpSize32, Requires<[Not64BitMode]>; } // mayStore, SchedRW let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { -def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[], - IIC_PUSH_MEM>, OpSize16; -def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[], - IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>; +def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>, + OpSize16; +def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>, + OpSize32, Requires<[Not64BitMode]>; } // mayLoad, mayStore, SchedRW } @@ -1249,71 +1247,69 @@ let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0, SchedRW = [WriteLoad] in { -def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, - OpSize16; -def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>, - OpSize32, Requires<[Not64BitMode]>; +def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize16; +def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, OpSize32, + Requires<[Not64BitMode]>; } let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0, SchedRW = [WriteStore] in { -def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>, - OpSize16; -def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>, - OpSize32, Requires<[Not64BitMode]>; +def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize16; +def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, OpSize32, + Requires<[Not64BitMode]>; } let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { let mayLoad = 1, SchedRW = [WriteLoad] in { -def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], - IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; -def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], - IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; +def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>; +def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>; } // mayLoad, SchedRW let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in -def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [], - IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>; +def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>, + OpSize32, Requires<[In64BitMode]>; let mayStore = 1, SchedRW = [WriteStore] in { -def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [], - IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; -def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [], - IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; +def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>; +def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, + OpSize32, Requires<[In64BitMode]>; } // mayStore, SchedRW let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { -def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [], - IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>; +def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>, + OpSize32, Requires<[In64BitMode]>; } // mayLoad, mayStore, SchedRW } let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, SchedRW = [WriteStore] in { def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), - "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32, + "push{q}\t$imm", []>, OpSize32, Requires<[In64BitMode]>; def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), - "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32, + "push{q}\t$imm", []>, OpSize32, Requires<[In64BitMode]>; } let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in -def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>, +def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in -def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>, +def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { -def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>, +def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", []>, OpSize32, Requires<[Not64BitMode]>; -def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>, +def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", []>, OpSize16, Requires<[Not64BitMode]>; } let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { -def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>, +def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", []>, OpSize32, Requires<[Not64BitMode]>; -def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>, +def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", []>, OpSize16, Requires<[Not64BitMode]>; } @@ -1322,116 +1318,116 @@ let Constraints = "$src = $dst", SchedRW = [WriteALU] in { def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "bswap{l}\t$dst", - [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB; + [(set GR32:$dst, (bswap GR32:$src))]>, OpSize32, TB; def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), "bswap{q}\t$dst", - [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB; + [(set GR64:$dst, (bswap GR64:$src))]>, TB; } // Constraints = "$src = $dst", SchedRW // Bit scan instructions. let Defs = [EFLAGS] in { def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), "bsf{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))], - IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteBitScan]>; + [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, + PS, OpSize16, Sched<[WriteBitScan]>; def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), "bsf{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))], - IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteBitScanLd]>; + [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, + PS, OpSize16, Sched<[WriteBitScanLd]>; def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), "bsf{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], - IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteBitScan]>; + [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, + PS, OpSize32, Sched<[WriteBitScan]>; def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), "bsf{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))], - IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteBitScanLd]>; + [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, + PS, OpSize32, Sched<[WriteBitScanLd]>; def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), "bsf{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))], - IIC_BIT_SCAN_REG>, PS, Sched<[WriteBitScan]>; + [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, + PS, Sched<[WriteBitScan]>; def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), "bsf{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))], - IIC_BIT_SCAN_MEM>, PS, Sched<[WriteBitScanLd]>; + [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, + PS, Sched<[WriteBitScanLd]>; def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), "bsr{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], - IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteBitScan]>; + [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, + PS, OpSize16, Sched<[WriteBitScan]>; def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), "bsr{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))], - IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteBitScanLd]>; + [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, + PS, OpSize16, Sched<[WriteBitScanLd]>; def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), "bsr{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], - IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteBitScan]>; + [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, + PS, OpSize32, Sched<[WriteBitScan]>; def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), "bsr{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))], - IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteBitScanLd]>; + [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, + PS, OpSize32, Sched<[WriteBitScanLd]>; def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), "bsr{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], - IIC_BIT_SCAN_REG>, PS, Sched<[WriteBitScan]>; + [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, + PS, Sched<[WriteBitScan]>; def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), "bsr{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))], - IIC_BIT_SCAN_MEM>, PS, Sched<[WriteBitScanLd]>; + [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, + PS, Sched<[WriteBitScanLd]>; } // Defs = [EFLAGS] let SchedRW = [WriteMicrocoded] in { let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in { def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), - "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; + "movsb\t{$src, $dst|$dst, $src}", []>; def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), - "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16; + "movsw\t{$src, $dst|$dst, $src}", []>, OpSize16; def MOVSL : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), - "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32; + "movs{l|d}\t{$src, $dst|$dst, $src}", []>, OpSize32; def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), - "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, + "movsq\t{$src, $dst|$dst, $src}", []>, Requires<[In64BitMode]>; } let Defs = [EDI], Uses = [AL,EDI,DF] in def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst), - "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>; + "stosb\t{%al, $dst|$dst, al}", []>; let Defs = [EDI], Uses = [AX,EDI,DF] in def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst), - "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16; + "stosw\t{%ax, $dst|$dst, ax}", []>, OpSize16; let Defs = [EDI], Uses = [EAX,EDI,DF] in def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst), - "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32; + "stos{l|d}\t{%eax, $dst|$dst, eax}", []>, OpSize32; let Defs = [RDI], Uses = [RAX,RDI,DF] in def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst), - "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>, + "stosq\t{%rax, $dst|$dst, rax}", []>, Requires<[In64BitMode]>; let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), - "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>; + "scasb\t{$dst, %al|al, $dst}", []>; let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), - "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16; + "scasw\t{$dst, %ax|ax, $dst}", []>, OpSize16; let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), - "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32; + "scas{l|d}\t{$dst, %eax|eax, $dst}", []>, OpSize32; let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), - "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>, + "scasq\t{$dst, %rax|rax, $dst}", []>, Requires<[In64BitMode]>; let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in { def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), - "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; + "cmpsb\t{$dst, $src|$src, $dst}", []>; def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), - "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16; + "cmpsw\t{$dst, $src|$src, $dst}", []>, OpSize16; def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), - "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32; + "cmps{l|d}\t{$dst, $src|$src, $dst}", []>, OpSize32; def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), - "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, + "cmpsq\t{$dst, $src|$src, $dst}", []>, Requires<[In64BitMode]>; } } // SchedRW @@ -1442,45 +1438,45 @@ def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), let SchedRW = [WriteMove] in { let hasSideEffects = 0 in { def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), - "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; + "mov{b}\t{$src, $dst|$dst, $src}", []>; def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), - "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), - "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), - "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; + "mov{q}\t{$src, $dst|$dst, $src}", []>; } let isReMaterializable = 1, isAsCheapAsAMove = 1 in { def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), "mov{b}\t{$src, $dst|$dst, $src}", - [(set GR8:$dst, imm:$src)], IIC_MOV>; + [(set GR8:$dst, imm:$src)]>; def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), "mov{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16; + [(set GR16:$dst, imm:$src)]>, OpSize16; def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), "mov{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, relocImm:$src)], IIC_MOV>, OpSize32; + [(set GR32:$dst, relocImm:$src)]>, OpSize32; def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), "mov{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>; + [(set GR64:$dst, i64immSExt32:$src)]>; } let isReMaterializable = 1 in { def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), "movabs{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, relocImm:$src)], IIC_MOV>; + [(set GR64:$dst, relocImm:$src)]>; } // Longer forms that use a ModR/M byte. Needed for disassembler let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), - "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, + "mov{b}\t{$src, $dst|$dst, $src}", []>, FoldGenData<"MOV8ri">; def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), - "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16, + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, FoldGenData<"MOV16ri">; def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), - "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32, + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, FoldGenData<"MOV32ri">; } } // SchedRW @@ -1488,16 +1484,16 @@ def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), let SchedRW = [WriteStore] in { def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), "mov{b}\t{$src, $dst|$dst, $src}", - [(store (i8 imm8_su:$src), addr:$dst)], IIC_MOV_MEM>; + [(store (i8 imm8_su:$src), addr:$dst)]>; def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), "mov{w}\t{$src, $dst|$dst, $src}", - [(store (i16 imm16_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16; + [(store (i16 imm16_su:$src), addr:$dst)]>, OpSize16; def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), "mov{l}\t{$src, $dst|$dst, $src}", - [(store (i32 imm32_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32; + [(store (i32 imm32_su:$src), addr:$dst)]>, OpSize32; def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), "mov{q}\t{$src, $dst|$dst, $src}", - [(store i64immSExt32_su:$src, addr:$dst)], IIC_MOV_MEM>, + [(store i64immSExt32_su:$src, addr:$dst)]>, Requires<[In64BitMode]>; } // SchedRW @@ -1509,60 +1505,60 @@ let SchedRW = [WriteALU] in { let mayLoad = 1 in { let Defs = [AL] in def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), - "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, + "mov{b}\t{$src, %al|al, $src}", []>, AdSize32; let Defs = [AX] in def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), - "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, + "mov{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize32; let Defs = [EAX] in def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), - "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, + "mov{l}\t{$src, %eax|eax, $src}", []>, OpSize32, AdSize32; let Defs = [RAX] in def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), - "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>, + "mov{q}\t{$src, %rax|rax, $src}", []>, AdSize32; let Defs = [AL] in def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), - "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16; + "mov{b}\t{$src, %al|al, $src}", []>, AdSize16; let Defs = [AX] in def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), - "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, + "mov{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize16; let Defs = [EAX] in def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), - "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, + "mov{l}\t{$src, %eax|eax, $src}", []>, AdSize16, OpSize32; } // mayLoad let mayStore = 1 in { let Uses = [AL] in def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst), - "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32; + "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize32; let Uses = [AX] in def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_16:$dst), - "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, + "mov{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize32; let Uses = [EAX] in def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_32:$dst), - "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, + "mov{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32, AdSize32; let Uses = [RAX] in def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs), (ins offset32_64:$dst), - "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>, + "mov{q}\t{%rax, $dst|$dst, rax}", []>, AdSize32; let Uses = [AL] in def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs), (ins offset16_8:$dst), - "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16; + "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize16; let Uses = [AX] in def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_16:$dst), - "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, + "mov{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize16; let Uses = [EAX] in def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst), - "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, + "mov{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32, AdSize16; } // mayStore @@ -1571,38 +1567,38 @@ def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst), let mayLoad = 1 in { let Defs = [AL] in def MOV8ao64 : Ii64<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), - "movabs{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, + "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64; let Defs = [AX] in def MOV16ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), - "movabs{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, + "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64; let Defs = [EAX] in def MOV32ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), - "movabs{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, + "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32, AdSize64; let Defs = [RAX] in def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), - "movabs{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>, + "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64; } // mayLoad let mayStore = 1 in { let Uses = [AL] in def MOV8o64a : Ii64<0xA2, RawFrmMemOffs, (outs), (ins offset64_8:$dst), - "movabs{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, + "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64; let Uses = [AX] in def MOV16o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_16:$dst), - "movabs{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, + "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64; let Uses = [EAX] in def MOV32o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_32:$dst), - "movabs{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, + "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32, AdSize64; let Uses = [RAX] in def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst), - "movabs{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>, + "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64; } // mayStore } // SchedRW @@ -1611,47 +1607,47 @@ def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst), let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, SchedRW = [WriteMove] in { def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), - "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, + "mov{b}\t{$src, $dst|$dst, $src}", []>, FoldGenData<"MOV8rr">; def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), - "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16, + "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, FoldGenData<"MOV16rr">; def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), - "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32, + "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, FoldGenData<"MOV32rr">; def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), - "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, + "mov{q}\t{$src, $dst|$dst, $src}", []>, FoldGenData<"MOV64rr">; } let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), "mov{b}\t{$src, $dst|$dst, $src}", - [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>; + [(set GR8:$dst, (loadi8 addr:$src))]>; def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), "mov{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16; + [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize16; def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), "mov{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; + [(set GR32:$dst, (loadi32 addr:$src))]>, OpSize32; def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), "mov{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>; + [(set GR64:$dst, (load addr:$src))]>; } let SchedRW = [WriteStore] in { def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), "mov{b}\t{$src, $dst|$dst, $src}", - [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; + [(store GR8:$src, addr:$dst)]>; def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), "mov{w}\t{$src, $dst|$dst, $src}", - [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16; + [(store GR16:$src, addr:$dst)]>, OpSize16; def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), "mov{l}\t{$src, $dst|$dst, $src}", - [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32; + [(store GR32:$src, addr:$dst)]>, OpSize32; def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), "mov{q}\t{$src, $dst|$dst, $src}", - [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>; + [(store GR64:$src, addr:$dst)]>; } // SchedRW // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so @@ -1661,19 +1657,19 @@ let isCodeGenOnly = 1 in { let hasSideEffects = 0 in def MOV8rr_NOREX : I<0x88, MRMDestReg, (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), - "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, + "mov{b}\t{$src, $dst|$dst, $src}", []>, Sched<[WriteMove]>; let mayStore = 1, hasSideEffects = 0 in def MOV8mr_NOREX : I<0x88, MRMDestMem, (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), - "mov{b}\t{$src, $dst|$dst, $src}", [], - IIC_MOV_MEM>, Sched<[WriteStore]>; + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteStore]>; let mayLoad = 1, hasSideEffects = 0, canFoldAsLoad = 1, isReMaterializable = 1 in def MOV8rm_NOREX : I<0x8A, MRMSrcMem, (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), - "mov{b}\t{$src, $dst|$dst, $src}", [], - IIC_MOV_MEM>, Sched<[WriteLoad]>; + "mov{b}\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteLoad]>; } @@ -1681,11 +1677,10 @@ def MOV8rm_NOREX : I<0x8A, MRMSrcMem, let SchedRW = [WriteALU] in { let Defs = [EFLAGS], Uses = [AH] in def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", - [(set EFLAGS, (X86sahf AH))], IIC_AHF>, - Requires<[HasLAHFSAHF]>; + [(set EFLAGS, (X86sahf AH))]>, + Requires<[HasLAHFSAHF]>; let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in -def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [], - IIC_AHF>, // AH = flags +def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags Requires<[HasLAHFSAHF]>; } // SchedRW @@ -1696,15 +1691,15 @@ let Defs = [EFLAGS] in { let SchedRW = [WriteALU] in { def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), "bt{w}\t{$src2, $src1|$src1, $src2}", - [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>, + [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize16, TB, NotMemoryFoldable; def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), "bt{l}\t{$src2, $src1|$src1, $src2}", - [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, + [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, OpSize32, TB, NotMemoryFoldable; def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), "bt{q}\t{$src2, $src1|$src1, $src2}", - [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB, + [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB, NotMemoryFoldable; } // SchedRW @@ -1717,190 +1712,180 @@ def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), "bt{w}\t{$src2, $src1|$src1, $src2}", - [], IIC_BT_MR - >, OpSize16, TB, NotMemoryFoldable; + []>, OpSize16, TB, NotMemoryFoldable; def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), "bt{l}\t{$src2, $src1|$src1, $src2}", - [], IIC_BT_MR - >, OpSize32, TB, NotMemoryFoldable; + []>, OpSize32, TB, NotMemoryFoldable; def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), "bt{q}\t{$src2, $src1|$src1, $src2}", - [], IIC_BT_MR - >, TB, NotMemoryFoldable; + []>, TB, NotMemoryFoldable; } let SchedRW = [WriteALU] in { def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), "bt{w}\t{$src2, $src1|$src1, $src2}", - [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))], - IIC_BT_RI>, OpSize16, TB; + [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>, + OpSize16, TB; def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), "bt{l}\t{$src2, $src1|$src1, $src2}", - [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))], - IIC_BT_RI>, OpSize32, TB; + [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, + OpSize32, TB; def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), "bt{q}\t{$src2, $src1|$src1, $src2}", - [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))], - IIC_BT_RI>, TB; + [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB; } // SchedRW // Note that these instructions aren't slow because that only applies when the // other operand is in a register. When it's an immediate, bt is still fast. let SchedRW = [WriteALU] in { def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), - "bt{w}\t{$src2, $src1|$src1, $src2}", - [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) - ], IIC_BT_MI>, OpSize16, TB; + "bt{w}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi16 addr:$src1), + i16immSExt8:$src2))]>, + OpSize16, TB; def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), - "bt{l}\t{$src2, $src1|$src1, $src2}", - [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) - ], IIC_BT_MI>, OpSize32, TB; + "bt{l}\t{$src2, $src1|$src1, $src2}", + [(set EFLAGS, (X86bt (loadi32 addr:$src1), + i32immSExt8:$src2))]>, + OpSize32, TB; def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), "bt{q}\t{$src2, $src1|$src1, $src2}", [(set EFLAGS, (X86bt (loadi64 addr:$src1), - i64immSExt8:$src2))], IIC_BT_MI>, TB, + i64immSExt8:$src2))]>, TB, Requires<[In64BitMode]>; } // SchedRW let hasSideEffects = 0 in { let SchedRW = [WriteALU], Constraints = "$src1 = $dst" in { def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), - "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB, NotMemoryFoldable; def BTC32rr : I<0xBB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), - "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB, NotMemoryFoldable; def BTC64rr : RI<0xBB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), - "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB, + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, NotMemoryFoldable; } // SchedRW let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), - "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB, NotMemoryFoldable; def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), - "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB, NotMemoryFoldable; def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), - "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB, + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, NotMemoryFoldable; } let SchedRW = [WriteALU], Constraints = "$src1 = $dst" in { def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), - "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, - OpSize16, TB; + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), - "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, - OpSize32, TB; + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; def BTC64ri8 : RIi8<0xBA, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), - "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; } // SchedRW let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), - "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, - OpSize16, TB; + "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), - "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, - OpSize32, TB; + "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), - "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB, + "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, Requires<[In64BitMode]>; } let SchedRW = [WriteALU], Constraints = "$src1 = $dst" in { def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), - "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB, NotMemoryFoldable; def BTR32rr : I<0xB3, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), - "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB, NotMemoryFoldable; def BTR64rr : RI<0xB3, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), - "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB, + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, NotMemoryFoldable; } // SchedRW let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), - "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB, NotMemoryFoldable; def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), - "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB, NotMemoryFoldable; def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), - "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB, + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, NotMemoryFoldable; } let SchedRW = [WriteALU], Constraints = "$src1 = $dst" in { def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), - "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; def BTR32ri8 : Ii8<0xBA, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), - "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), - "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; } // SchedRW let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), - "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, + "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), - "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, + "btr{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), - "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB, + "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, Requires<[In64BitMode]>; } let SchedRW = [WriteALU], Constraints = "$src1 = $dst" in { def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), - "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB, NotMemoryFoldable; def BTS32rr : I<0xAB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), - "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB, NotMemoryFoldable; def BTS64rr : RI<0xAB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), - "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB, + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, NotMemoryFoldable; } // SchedRW let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), - "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB, NotMemoryFoldable; def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), - "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB, NotMemoryFoldable; def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), - "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB, + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, NotMemoryFoldable; } let SchedRW = [WriteALU], Constraints = "$src1 = $dst" in { def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), - "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, - OpSize16, TB; + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), - "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, - OpSize32, TB; + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; def BTS64ri8 : RIi8<0xBA, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), - "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; } // SchedRW let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), - "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, - OpSize16, TB; + "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), - "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, - OpSize32, TB; + "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), - "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB, + "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, Requires<[In64BitMode]>; } } // hasSideEffects = 0 @@ -1913,135 +1898,124 @@ def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), // Atomic swap. These are just normal xchg instructions. But since a memory // operand is referenced, the atomicity is ensured. -multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag, - InstrItinClass itin> { +multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag> { let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr), !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), [(set GR8:$dst, - (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], - itin>; + (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>; def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr), !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), [(set GR16:$dst, - (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], - itin>, OpSize16; + (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>, + OpSize16; def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr), !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), [(set GR32:$dst, - (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], - itin>, OpSize32; + (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>, + OpSize32; def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val, i64mem:$ptr), !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), [(set GR64:$dst, - (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], - itin>; + (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>; } } -defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>; +defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">; // Swap between registers. let SchedRW = [WriteALU] in { let Constraints = "$val = $dst" in { def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), - "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; + "xchg{b}\t{$val, $src|$src, $val}", []>; def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), - "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, + "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize16; def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), - "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, + "xchg{l}\t{$val, $src|$src, $val}", []>, OpSize32; def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), - "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; + "xchg{q}\t{$val, $src|$src, $val}", []>; } // Swap between EAX and other registers. let Uses = [AX], Defs = [AX] in def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), - "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16; + "xchg{w}\t{$src, %ax|ax, $src}", []>, OpSize16; let Uses = [EAX], Defs = [EAX] in def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), - "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, + "xchg{l}\t{$src, %eax|eax, $src}", []>, OpSize32; let Uses = [RAX], Defs = [RAX] in def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), - "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>; + "xchg{q}\t{$src, %rax|rax, $src}", []>; } // SchedRW let SchedRW = [WriteALU] in { def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), - "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; + "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB; def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), - "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, + "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), - "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, + "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), - "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; + "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB; } // SchedRW let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), - "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; + "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB; def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), - "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, + "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), - "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, + "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), - "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; + "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB; } let SchedRW = [WriteALU] in { def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), - "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], - IIC_CMPXCHG_REG8>, TB; + "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), - "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], - IIC_CMPXCHG_REG>, TB, OpSize16; + "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), - "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], - IIC_CMPXCHG_REG>, TB, OpSize32; + "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), - "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], - IIC_CMPXCHG_REG>, TB; + "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB; } // SchedRW let SchedRW = [WriteALULd, WriteRMW] in { let mayLoad = 1, mayStore = 1 in { def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), - "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], - IIC_CMPXCHG_MEM8>, TB; + "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), - "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], - IIC_CMPXCHG_MEM>, TB, OpSize16; + "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), - "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], - IIC_CMPXCHG_MEM>, TB, OpSize32; + "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), - "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], - IIC_CMPXCHG_MEM>, TB; + "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB; } let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), - "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB; + "cmpxchg8b\t$dst", []>, TB; let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), - "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>, + "cmpxchg16b\t$dst", []>, TB, Requires<[HasCmpxchg16b, In64BitMode]>; } // SchedRW @@ -2077,89 +2051,85 @@ def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; let SchedRW = [WriteMicrocoded] in { let Defs = [AL,ESI], Uses = [ESI,DF] in def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), - "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>; + "lodsb\t{$src, %al|al, $src}", []>; let Defs = [AX,ESI], Uses = [ESI,DF] in def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), - "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16; + "lodsw\t{$src, %ax|ax, $src}", []>, OpSize16; let Defs = [EAX,ESI], Uses = [ESI,DF] in def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), - "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32; + "lods{l|d}\t{$src, %eax|eax, $src}", []>, OpSize32; let Defs = [RAX,ESI], Uses = [ESI,DF] in def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), - "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>, + "lodsq\t{$src, %rax|rax, $src}", []>, Requires<[In64BitMode]>; } let SchedRW = [WriteSystem] in { let Defs = [ESI], Uses = [DX,ESI,DF] in { def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), - "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>; + "outsb\t{$src, %dx|dx, $src}", []>; def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), - "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16; + "outsw\t{$src, %dx|dx, $src}", []>, OpSize16; def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), - "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32; + "outs{l|d}\t{$src, %dx|dx, $src}", []>, OpSize32; } let Defs = [EDI], Uses = [DX,EDI,DF] in { def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst), - "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>; + "insb\t{%dx, $dst|$dst, dx}", []>; def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst), - "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16; + "insw\t{%dx, $dst|$dst, dx}", []>, OpSize16; def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst), - "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32; + "ins{l|d}\t{%dx, $dst|$dst, dx}", []>, OpSize32; } } // EFLAGS management instructions. let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { -def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC_CMC_STC>; -def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_CLC_CMC_STC>; -def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CLC_CMC_STC>; +def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; +def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; +def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; } // DF management instructions. -// FIXME: These are a bit more expensive than CLC and STC. We should consider -// adjusting their schedule bucket. let SchedRW = [WriteALU], Defs = [DF] in { -def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>; -def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>; +def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; +def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; } - // Table lookup instructions let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in -def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>, - Sched<[WriteLoad]>; +def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>, Sched<[WriteLoad]>; let SchedRW = [WriteMicrocoded] in { // ASCII Adjust After Addition let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in -def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>, +def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[Not64BitMode]>; // ASCII Adjust AX Before Division let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), - "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>; + "aad\t$src", []>, Requires<[Not64BitMode]>; // ASCII Adjust AX After Multiply let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), - "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>; + "aam\t$src", []>, Requires<[Not64BitMode]>; // ASCII Adjust AL After Subtraction - sets let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in -def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>, +def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[Not64BitMode]>; // Decimal Adjust AL after Addition let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in -def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>, +def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[Not64BitMode]>; // Decimal Adjust AL after Subtraction let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in -def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>, +def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[Not64BitMode]>; } // SchedRW @@ -2167,19 +2137,19 @@ let SchedRW = [WriteSystem] in { // Check Array Index Against Bounds // Note: "bound" does not have reversed operands in at&t syntax. def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), - "bound\t$dst, $src", [], IIC_BOUND>, OpSize16, + "bound\t$dst, $src", []>, OpSize16, Requires<[Not64BitMode]>; def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), - "bound\t$dst, $src", [], IIC_BOUND>, OpSize32, + "bound\t$dst, $src", []>, OpSize32, Requires<[Not64BitMode]>; // Adjust RPL Field of Segment Selector def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), - "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>, + "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[Not64BitMode]>; let mayStore = 1 in def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), - "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>, + "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[Not64BitMode]>; } // SchedRW @@ -2190,29 +2160,29 @@ let Predicates = [HasMOVBE] in { let SchedRW = [WriteALULd] in { def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), "movbe{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>, + [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, OpSize16, T8PS; def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), "movbe{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>, + [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, OpSize32, T8PS; def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), "movbe{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>, + [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, T8PS; } let SchedRW = [WriteStore] in { def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), "movbe{w}\t{$src, $dst|$dst, $src}", - [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>, + [(store (bswap GR16:$src), addr:$dst)]>, OpSize16, T8PS; def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), "movbe{l}\t{$src, $dst|$dst, $src}", - [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>, + [(store (bswap GR32:$src), addr:$dst)]>, OpSize32, T8PS; def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), "movbe{q}\t{$src, $dst|$dst, $src}", - [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>, + [(store (bswap GR64:$src), addr:$dst)]>, T8PS; } } @@ -2222,33 +2192,26 @@ let Predicates = [HasMOVBE] in { // let Predicates = [HasRDRAND], Defs = [EFLAGS], SchedRW = [WriteSystem] in { def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), - "rdrand{w}\t$dst", - [(set GR16:$dst, EFLAGS, (X86rdrand))], IIC_RDRAND>, + "rdrand{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, PS; def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), - "rdrand{l}\t$dst", - [(set GR32:$dst, EFLAGS, (X86rdrand))], IIC_RDRAND>, + "rdrand{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, PS; def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), - "rdrand{q}\t$dst", - [(set GR64:$dst, EFLAGS, (X86rdrand))], IIC_RDRAND>, PS; + "rdrand{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86rdrand))]>, + PS; } //===----------------------------------------------------------------------===// // RDSEED Instruction // let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in { - def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), - "rdseed{w}\t$dst", - [(set GR16:$dst, EFLAGS, (X86rdseed))], IIC_RDSEED>, - OpSize16, PS; - def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), - "rdseed{l}\t$dst", - [(set GR32:$dst, EFLAGS, (X86rdseed))], IIC_RDSEED>, - OpSize32, PS; - def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), - "rdseed{q}\t$dst", - [(set GR64:$dst, EFLAGS, (X86rdseed))], IIC_RDSEED>, PS; + def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), "rdseed{w}\t$dst", + [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, PS; + def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), "rdseed{l}\t$dst", + [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, PS; + def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdseed{q}\t$dst", + [(set GR64:$dst, EFLAGS, (X86rdseed))]>, PS; } //===----------------------------------------------------------------------===// @@ -2257,33 +2220,30 @@ let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in { let Predicates = [HasLZCNT], Defs = [EFLAGS] in { def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), "lzcnt{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)], - IIC_LZCNT_RR>, XS, OpSize16, Sched<[WriteLZCNT]>; + [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, + XS, OpSize16, Sched<[WriteLZCNT]>; def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), "lzcnt{w}\t{$src, $dst|$dst, $src}", [(set GR16:$dst, (ctlz (loadi16 addr:$src))), - (implicit EFLAGS)], IIC_LZCNT_RM>, XS, OpSize16, - Sched<[WriteLZCNTLd]>; + (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteLZCNTLd]>; def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), "lzcnt{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)], - IIC_LZCNT_RR>, XS, OpSize32, Sched<[WriteLZCNT]>; + [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, + XS, OpSize32, Sched<[WriteLZCNT]>; def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), "lzcnt{l}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (ctlz (loadi32 addr:$src))), - (implicit EFLAGS)], IIC_LZCNT_RM>, XS, OpSize32, - Sched<[WriteLZCNTLd]>; + (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteLZCNTLd]>; def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), "lzcnt{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)], - IIC_LZCNT_RR>, XS, Sched<[WriteLZCNT]>; + [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, + XS, Sched<[WriteLZCNT]>; def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), "lzcnt{q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (ctlz (loadi64 addr:$src))), - (implicit EFLAGS)], IIC_LZCNT_RM>, XS, - Sched<[WriteLZCNTLd]>; + (implicit EFLAGS)]>, XS, Sched<[WriteLZCNTLd]>; } //===----------------------------------------------------------------------===// @@ -2292,33 +2252,30 @@ let Predicates = [HasLZCNT], Defs = [EFLAGS] in { let Predicates = [HasBMI], Defs = [EFLAGS] in { def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), "tzcnt{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)], - IIC_TZCNT_RR>, XS, OpSize16, Sched<[WriteTZCNT]>; + [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, + XS, OpSize16, Sched<[WriteTZCNT]>; def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), "tzcnt{w}\t{$src, $dst|$dst, $src}", [(set GR16:$dst, (cttz (loadi16 addr:$src))), - (implicit EFLAGS)], IIC_TZCNT_RM>, XS, OpSize16, - Sched<[WriteTZCNTLd]>; + (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteTZCNTLd]>; def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), "tzcnt{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)], - IIC_TZCNT_RR>, XS, OpSize32, Sched<[WriteTZCNT]>; + [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, + XS, OpSize32, Sched<[WriteTZCNT]>; def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), "tzcnt{l}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (cttz (loadi32 addr:$src))), - (implicit EFLAGS)], IIC_TZCNT_RM>, XS, OpSize32, - Sched<[WriteTZCNTLd]>; + (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteTZCNTLd]>; def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), "tzcnt{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)], - IIC_TZCNT_RR>, XS, Sched<[WriteTZCNT]>; + [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, + XS, Sched<[WriteTZCNT]>; def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), "tzcnt{q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (cttz (loadi64 addr:$src))), - (implicit EFLAGS)], IIC_TZCNT_RM>, XS, - Sched<[WriteTZCNTLd]>; + (implicit EFLAGS)]>, XS, Sched<[WriteTZCNTLd]>; } multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, @@ -2587,28 +2544,24 @@ let Predicates = [HasTBM] in { let Predicates = [HasLWP], SchedRW = [WriteSystem] in { def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", - [(int_x86_llwpcb GR32:$src)], IIC_LWP>, - XOP, XOP9; + [(int_x86_llwpcb GR32:$src)]>, XOP, XOP9; def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", - [(set GR32:$dst, (int_x86_slwpcb))], IIC_LWP>, - XOP, XOP9; + [(set GR32:$dst, (int_x86_slwpcb))]>, XOP, XOP9; def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", - [(int_x86_llwpcb GR64:$src)], IIC_LWP>, - XOP, XOP9, VEX_W; + [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, VEX_W; def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", - [(set GR64:$dst, (int_x86_slwpcb))], IIC_LWP>, - XOP, XOP9, VEX_W; + [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, VEX_W; multiclass lwpins_intr<RegisterClass RC> { def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", - [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, imm:$cntl))], IIC_LWP>, + [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, imm:$cntl))]>, XOP_4V, XOPA; let mayLoad = 1 in def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", - [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), imm:$cntl))], IIC_LWP>, + [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), imm:$cntl))]>, XOP_4V, XOPA; } @@ -2620,12 +2573,11 @@ let Defs = [EFLAGS] in { multiclass lwpval_intr<RegisterClass RC, Intrinsic Int> { def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", - [(Int RC:$src0, GR32:$src1, imm:$cntl)], IIC_LWP>, - XOP_4V, XOPA; + [(Int RC:$src0, GR32:$src1, imm:$cntl)]>, XOP_4V, XOPA; let mayLoad = 1 in def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", - [(Int RC:$src0, (loadi32 addr:$src1), imm:$cntl)], IIC_LWP>, + [(Int RC:$src0, (loadi32 addr:$src1), imm:$cntl)]>, XOP_4V, XOPA; } @@ -2645,13 +2597,13 @@ let SchedRW = [ WriteSystem ] in { } let Uses = [ EAX, ECX, EDX ] in { - def MONITORXrrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", [], IIC_SSE_MONITORX>, + def MONITORXrrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, TB, Requires<[ HasMWAITX ]>; } let Uses = [ ECX, EAX, EBX ] in { def MWAITXrrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", - [(int_x86_mwaitx ECX, EAX, EBX)], IIC_SSE_MWAITX>, + [(int_x86_mwaitx ECX, EAX, EBX)]>, TB, Requires<[ HasMWAITX ]>; } } // SchedRW @@ -2671,7 +2623,7 @@ def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>, // let SchedRW = [WriteSystem] in { let Uses = [EAX] in - def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", [], IIC_SSE_CLZERO>, + def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, TB, Requires<[HasCLZERO]>; let usesCustomInserter = 1 in { @@ -2747,12 +2699,11 @@ let Predicates = [HasTBM] in { let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), - "clflushopt\t$src", [(int_x86_clflushopt addr:$src)], - IIC_SSE_PREFETCH>, PD; + "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD; let Predicates = [HasCLWB], SchedRW = [WriteLoad] in def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", - [(int_x86_clwb addr:$src)], IIC_SSE_PREFETCH>, PD; + [(int_x86_clwb addr:$src)]>, PD; //===----------------------------------------------------------------------===// // Subsystems. diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 361f2a9ad34..7a1876f7f7a 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -3488,46 +3488,39 @@ let Predicates = [UseSSE2] in { // Prefetch intrinsic. let Predicates = [HasSSEPrefetch], SchedRW = [WriteLoad] in { def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src), - "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))], - IIC_SSE_PREFETCH>, TB; + "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>, TB; def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src), - "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))], - IIC_SSE_PREFETCH>, TB; + "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>, TB; def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src), - "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))], - IIC_SSE_PREFETCH>, TB; + "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>, TB; def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src), - "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))], - IIC_SSE_PREFETCH>, TB; + "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>, TB; } // FIXME: How should flush instruction be modeled? let SchedRW = [WriteLoad] in { // Flush cache def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src), - "clflush\t$src", [(int_x86_sse2_clflush addr:$src)], - IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>; + "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>, + PS, Requires<[HasSSE2]>; } let SchedRW = [WriteNop] in { // Pause. This "instruction" is encoded as "rep; nop", so even though it // was introduced with SSE2, it's backward compatible. def PAUSE : I<0x90, RawFrm, (outs), (ins), - "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>, OBXS; + "pause", [(int_x86_sse2_pause)]>, OBXS; } let SchedRW = [WriteFence] in { // Load, store, and memory fence // TODO: As with mfence, we may want to ease the availablity of sfence/lfence // to include any 64-bit target. -def SFENCE : I<0xAE, MRM_F8, (outs), (ins), - "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>, +def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>, PS, Requires<[HasSSE1]>; -def LFENCE : I<0xAE, MRM_E8, (outs), (ins), - "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>, +def LFENCE : I<0xAE, MRM_E8, (outs), (ins), "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>; -def MFENCE : I<0xAE, MRM_F0, (outs), (ins), - "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>, +def MFENCE : I<0xAE, MRM_F0, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasMFence]>; } // SchedRW @@ -3538,18 +3531,18 @@ def : Pat<(X86MFence), (MFENCE)>; //===----------------------------------------------------------------------===// def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src), - "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)], - IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>, VEX_WIG; + "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, + VEX, Sched<[WriteLoad]>, VEX_WIG; def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst), - "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)], - IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>, VEX_WIG; + "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, + VEX, Sched<[WriteStore]>, VEX_WIG; def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src), - "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)], - IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>; + "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, + TB, Sched<[WriteLoad]>; def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst), - "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)], - IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>; + "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, + TB, Sched<[WriteStore]>; //===---------------------------------------------------------------------===// // SSE2 - Move Aligned/Unaligned Packed Integer Instructions @@ -5306,13 +5299,12 @@ def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3), } let Uses = [EAX, ECX, EDX] in -def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>, - TB, Requires<[HasSSE3]>; +def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, + TB, Requires<[HasSSE3]>; let Uses = [ECX, EAX] in def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", - [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>, - TB, Requires<[HasSSE3]>; + [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>; } // SchedRW def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>; diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td index 308b892982c..0244c277c03 100644 --- a/llvm/lib/Target/X86/X86Schedule.td +++ b/llvm/lib/Target/X86/X86Schedule.td @@ -378,20 +378,6 @@ def IIC_SSE_PMADD : InstrItinClass; def IIC_SSE_PMULHRSW : InstrItinClass; def IIC_SSE_PALIGNRR : InstrItinClass; def IIC_SSE_PALIGNRM : InstrItinClass; -def IIC_SSE_MWAIT : InstrItinClass; -def IIC_SSE_MONITOR : InstrItinClass; -def IIC_SSE_MWAITX : InstrItinClass; -def IIC_SSE_MONITORX : InstrItinClass; -def IIC_SSE_CLZERO : InstrItinClass; - -def IIC_SSE_PREFETCH : InstrItinClass; -def IIC_SSE_PAUSE : InstrItinClass; -def IIC_SSE_LFENCE : InstrItinClass; -def IIC_SSE_MFENCE : InstrItinClass; -def IIC_SSE_SFENCE : InstrItinClass; -def IIC_SSE_LDMXCSR : InstrItinClass; -def IIC_SSE_STMXCSR : InstrItinClass; - def IIC_SSE_CVT_PD_RR : InstrItinClass; def IIC_SSE_CVT_PD_RM : InstrItinClass; def IIC_SSE_CVT_PS_RR : InstrItinClass; @@ -407,80 +393,6 @@ def IIC_SSE_CVT_SD2SI_RR : InstrItinClass; def IIC_AVX_ZERO : InstrItinClass; -def IIC_CMPX_LOCK : InstrItinClass; -def IIC_CMPX_LOCK_8 : InstrItinClass; -def IIC_CMPX_LOCK_8B : InstrItinClass; -def IIC_CMPX_LOCK_16B : InstrItinClass; - -def IIC_XADD_LOCK_MEM : InstrItinClass; -def IIC_XADD_LOCK_MEM8 : InstrItinClass; - -// System instructions -def IIC_RDRAND : InstrItinClass; -def IIC_RDSEED : InstrItinClass; -def IIC_INS : InstrItinClass; -def IIC_LWP : InstrItinClass; -def IIC_ENTER : InstrItinClass; -def IIC_LEAVE : InstrItinClass; -def IIC_POP_MEM : InstrItinClass; -def IIC_POP_REG16 : InstrItinClass; -def IIC_POP_REG : InstrItinClass; -def IIC_POP_F : InstrItinClass; -def IIC_POP_FD : InstrItinClass; -def IIC_POP_A : InstrItinClass; -def IIC_PUSH_IMM : InstrItinClass; -def IIC_PUSH_MEM : InstrItinClass; -def IIC_PUSH_REG : InstrItinClass; -def IIC_PUSH_F : InstrItinClass; -def IIC_PUSH_A : InstrItinClass; -def IIC_BSWAP : InstrItinClass; -def IIC_BIT_SCAN_MEM : InstrItinClass; -def IIC_BIT_SCAN_REG : InstrItinClass; -def IIC_LZCNT_RR : InstrItinClass; -def IIC_LZCNT_RM : InstrItinClass; -def IIC_TZCNT_RR : InstrItinClass; -def IIC_TZCNT_RM : InstrItinClass; -def IIC_MOVS : InstrItinClass; -def IIC_STOS : InstrItinClass; -def IIC_SCAS : InstrItinClass; -def IIC_CMPS : InstrItinClass; -def IIC_MOV : InstrItinClass; -def IIC_MOV_MEM : InstrItinClass; -def IIC_AHF : InstrItinClass; -def IIC_BT_MI : InstrItinClass; -def IIC_BT_MR : InstrItinClass; -def IIC_BT_RI : InstrItinClass; -def IIC_BT_RR : InstrItinClass; -def IIC_BTX_MI : InstrItinClass; -def IIC_BTX_MR : InstrItinClass; -def IIC_BTX_RI : InstrItinClass; -def IIC_BTX_RR : InstrItinClass; -def IIC_XCHG_REG : InstrItinClass; -def IIC_XCHG_MEM : InstrItinClass; -def IIC_XADD_REG : InstrItinClass; -def IIC_XADD_MEM : InstrItinClass; -def IIC_CMPXCHG_MEM : InstrItinClass; -def IIC_CMPXCHG_REG : InstrItinClass; -def IIC_CMPXCHG_MEM8 : InstrItinClass; -def IIC_CMPXCHG_REG8 : InstrItinClass; -def IIC_CMPXCHG_8B : InstrItinClass; -def IIC_CMPXCHG_16B : InstrItinClass; -def IIC_LODS : InstrItinClass; -def IIC_OUTS : InstrItinClass; -def IIC_CLC_CMC_STC : InstrItinClass; -def IIC_CLD : InstrItinClass; -def IIC_STD : InstrItinClass; -def IIC_XLAT : InstrItinClass; -def IIC_AAA : InstrItinClass; -def IIC_AAD : InstrItinClass; -def IIC_AAM : InstrItinClass; -def IIC_AAS : InstrItinClass; -def IIC_DAA : InstrItinClass; -def IIC_DAS : InstrItinClass; -def IIC_BOUND : InstrItinClass; -def IIC_ARPL_REG : InstrItinClass; -def IIC_ARPL_MEM : InstrItinClass; -def IIC_MOVBE : InstrItinClass; def IIC_AES : InstrItinClass; def IIC_BLEND_MEM : InstrItinClass; def IIC_BLEND_NOMEM : InstrItinClass; |
