diff options
| -rw-r--r-- | llvm/include/llvm/CodeGen/MachineMemOperand.h | 25 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 22 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.h | 6 |
4 files changed, 17 insertions, 38 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineMemOperand.h b/llvm/include/llvm/CodeGen/MachineMemOperand.h index 40b0ae55b57..5fa7058733b 100644 --- a/llvm/include/llvm/CodeGen/MachineMemOperand.h +++ b/llvm/include/llvm/CodeGen/MachineMemOperand.h @@ -89,32 +89,27 @@ struct MachinePointerInfo { /// class MachineMemOperand { public: - // This is the number of bits we need to represent flags. - static LLVM_CONSTEXPR unsigned MOMaxBits = 8; - - // Target hints allow target passes to annotate memory operations. - static LLVM_CONSTEXPR unsigned MOTargetStartBit = 5; - static LLVM_CONSTEXPR unsigned MOTargetNumBits = 3; - /// Flags values. These may be or'd together. enum Flags : uint16_t { // No flags set. MONone = 0, /// The memory access reads data. - MOLoad = 1, + MOLoad = 1u << 0, /// The memory access writes data. - MOStore = 2, + MOStore = 1u << 1, /// The memory access is volatile. - MOVolatile = 4, + MOVolatile = 1u << 2, /// The memory access is non-temporal. - MONonTemporal = 8, + MONonTemporal = 1u << 3, /// The memory access is invariant. - MOInvariant = 16, + MOInvariant = 1u << 4, - // Maximum MemOperandFlag value (inclusive). - MOMaxFlag = (1 << MOMaxBits) - 1, + // Reserved for use by target-specific passes. + MOTargetFlag1 = 1u << 5, + MOTargetFlag2 = 1u << 6, + MOTargetFlag3 = 1u << 7, - LLVM_MARK_AS_BITMASK_ENUM(MOMaxFlag) + LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ MOTargetFlag3) }; private: diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 3dbbd8780c3..ead239f604d 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -503,8 +503,6 @@ MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f, const MDNode *Ranges) : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1), AAInfo(AAInfo), Ranges(Ranges) { - assert(MOMaxFlag == (1 << MOMaxBits) - 1 && - "MOMaxFlag and MOMaxBits have fallen out of sync."); assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() || isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) && "invalid pointer value"); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index f1152155b3f..aa804240dfc 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -29,6 +29,9 @@ using namespace llvm; #define GET_INSTRINFO_CTOR_DTOR #include "AArch64GenInstrInfo.inc" +static constexpr MachineMemOperand::Flags MOSuppressPair = + MachineMemOperand::MOTargetFlag1; + AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI) : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP), RI(STI.getTargetTriple()), Subtarget(STI) {} @@ -1449,27 +1452,16 @@ bool AArch64InstrInfo::isScaledAddr(const MachineInstr &MI) const { /// Check all MachineMemOperands for a hint to suppress pairing. bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr &MI) const { - static_assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits), - "Too many target MO flags"); - for (auto *MM : MI.memoperands()) { - if (MM->getFlags() & - (MOSuppressPair << MachineMemOperand::MOTargetStartBit)) { - return true; - } - } - return false; + return any_of(MI.memoperands(), [](MachineMemOperand *MMO) { + return MMO->getFlags() & MOSuppressPair; + }); } /// Set a flag on the first MachineMemOperand to suppress pairing. void AArch64InstrInfo::suppressLdStPair(MachineInstr &MI) const { if (MI.memoperands_empty()) return; - - static_assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits), - "Too many target MO flags"); - (*MI.memoperands_begin()) - ->setFlags(static_cast<MachineMemOperand::Flags>( - MOSuppressPair << MachineMemOperand::MOTargetStartBit)); + (*MI.memoperands_begin())->setFlags(MOSuppressPair); } bool AArch64InstrInfo::isUnscaledLdSt(unsigned Opc) const { diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index fc0696c9db7..0e67da754a5 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -28,12 +28,6 @@ class AArch64Subtarget; class AArch64TargetMachine; class AArch64InstrInfo : public AArch64GenInstrInfo { - // Reserve bits in the MachineMemOperand target hint flags, starting at 1. - // They will be shifted into MOTargetHintStart when accessed. - enum TargetMemOperandFlags { - MOSuppressPair = 1 - }; - const AArch64RegisterInfo RI; const AArch64Subtarget &Subtarget; |
