diff options
| -rw-r--r-- | clang/docs/ReleaseNotes.rst | 3 | ||||
| -rw-r--r-- | lld/docs/ReleaseNotes.rst | 8 | ||||
| -rw-r--r-- | llvm/docs/ReleaseNotes.rst | 18 |
3 files changed, 27 insertions, 2 deletions
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 7bc3a15b213..c0e1ffde2a6 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -110,6 +110,9 @@ Non-comprehensive list of changes in this release Clang-specific flag ``-flax-vector-conversions=all``. In a future release of Clang, we intend to change the default to ``-fno-lax-vector-conversions``. +* Improved support for ``octeon`` MIPS-family CPU. Added ``octeon+`` to + the list of of CPUs accepted by the driver. + New Compiler Flags ------------------ diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst index bc16417646c..2829e14d1ee 100644 --- a/lld/docs/ReleaseNotes.rst +++ b/lld/docs/ReleaseNotes.rst @@ -30,6 +30,14 @@ ELF Improvements with GNU now. (`r375051 <https://github.com/llvm/llvm-project/commit/48993d5ab9413f0e5b94dfa292a233ce55b09e3e>`_) +* New ``elf32btsmipn32_fbsd`` and ``elf32ltsmipn32_fbsd`` emulations + are supported. + +* Relax MIPS ``jalr``and ``jr`` instructions marked by the ``R_MIPS_JALR`` + relocation. + +* Reduced size of linked MIPS binaries. + COFF Improvements ----------------- diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index f48fae25a08..dd6490379af 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -124,8 +124,22 @@ Changes to the ARM Backend Changes to the MIPS Target -------------------------- - During this release ... - +* Improved support for ``octeon`` and added support for ``octeon+`` + MIPS-family CPU. +* ``min``, ``max``, ``umin``, ``umax`` atomics now supported on MIPS targets. +* Now PC-relative relocations are generated for ``.eh_frame`` sections when + possible. That allows to link MIPS binaries without having to pass the + ``-Wl,-z,notext`` option. +* Fix evaluating J-format branch (``j``, ``jal``, ...) targets when the + instruction is not in the first 256 MB region. +* Fixed ``jal``, ``sc``, ``scs``, ``ll``, ``lld``, ``la``, ``lw``, ``sw`` + instructions expanding. Now they accept more types of expression as arguments, + correctly handle load/store for ``XGOT`` model, expand using less instructions + or registers. +* Initial MIPS support has been added to ``llvm-exegesis``. +* Generates ``_mcount`` calls using proper MIPS ABI. +* Improved support of GlobalISel instruction selection framework. This feature + is still in experimental state for MIPS targets though. Changes to the PowerPC Target ----------------------------- |
