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-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp5
-rw-r--r--llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll28
2 files changed, 31 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
index b427de1d9da..2e8db08830e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
@@ -146,9 +146,10 @@ public:
Value *AMDGPUCodeGenPrepare::copyFlags(
const BinaryOperator &I, Value *V) const {
- assert(isa<BinaryOperator>(V) && "V must be binary operation");
+ BinaryOperator *BinOp = dyn_cast<BinaryOperator>(V);
+ if (!BinOp) // Possibly constant expression.
+ return V;
- BinaryOperator *BinOp = cast<BinaryOperator>(V);
if (isa<OverflowingBinaryOperator>(BinOp)) {
BinOp->setHasNoSignedWrap(I.hasNoSignedWrap());
BinOp->setHasNoUnsignedWrap(I.hasNoUnsignedWrap());
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll
index 5444b74ac4f..13e4192ccd7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll
@@ -533,6 +533,27 @@ define i16 @add_i16(i16 %a, i16 %b) {
ret i16 %r
}
+; GCN-LABEL: @constant_add_i16(
+; VI: ret i16 3
+define i16 @constant_add_i16() {
+ %r = add i16 1, 2
+ ret i16 %r
+}
+
+; GCN-LABEL: @constant_add_nsw_i16(
+; VI: ret i16 3
+define i16 @constant_add_nsw_i16() {
+ %r = add nsw i16 1, 2
+ ret i16 %r
+}
+
+; GCN-LABEL: @constant_add_nuw_i16(
+; VI: ret i16 3
+define i16 @constant_add_nuw_i16() {
+ %r = add nsw i16 1, 2
+ ret i16 %r
+}
+
; GCN-LABEL: @add_nsw_i16(
; SI: %r = add nsw i16 %a, %b
; SI-NEXT: ret i16 %r
@@ -806,6 +827,13 @@ define i16 @ashr_exact_i16(i16 %a, i16 %b) {
ret i16 %r
}
+; GCN-LABEL: @constant_lshr_exact_i16(
+; VI: ret i16 2
+define i16 @constant_lshr_exact_i16(i16 %a, i16 %b) {
+ %r = lshr exact i16 4, 1
+ ret i16 %r
+}
+
; GCN-LABEL: @and_i16(
; SI: %r = and i16 %a, %b
; SI-NEXT: ret i16 %r
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