diff options
| -rw-r--r-- | llvm/include/llvm/CodeGen/MachineOperand.h | 3 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 25 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/commute-compares.ll | 15 |
4 files changed, 44 insertions, 9 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineOperand.h b/llvm/include/llvm/CodeGen/MachineOperand.h index df143602a47..05e6f466184 100644 --- a/llvm/include/llvm/CodeGen/MachineOperand.h +++ b/llvm/include/llvm/CodeGen/MachineOperand.h @@ -593,6 +593,9 @@ public: /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand. void ChangeToMCSymbol(MCSymbol *Sym); + /// Replace this operand with a frame index. + void ChangeToFrameIndex(int Idx); + /// ChangeToRegister - Replace this operand with a new register operand of /// the specified value. If an operand is known to be an register already, /// the setReg method should be used. diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index cc33b1efdbf..e2bbe3cb870 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -175,6 +175,16 @@ void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) { Contents.Sym = Sym; } +void MachineOperand::ChangeToFrameIndex(int Idx) { + assert((!isReg() || !isTied()) && + "Cannot change a tied operand into a FrameIndex"); + + removeRegFromUses(); + + OpKind = MO_FrameIndex; + setIndex(Idx); +} + /// ChangeToRegister - Replace this operand with a new register operand of /// the specified value. If an operand is known to be an register already, /// the setReg method should be used. diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 7748fbb1a29..39175a1910d 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -937,17 +937,24 @@ bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI, static MachineInstr *swapRegAndNonRegOperand(MachineInstr &MI, MachineOperand &RegOp, - MachineOperand &ImmOp) { - // TODO: Handle other immediate like types. - if (!ImmOp.isImm()) + MachineOperand &NonRegOp) { + unsigned Reg = RegOp.getReg(); + unsigned SubReg = RegOp.getSubReg(); + bool IsKill = RegOp.isKill(); + bool IsDead = RegOp.isDead(); + bool IsUndef = RegOp.isUndef(); + bool IsDebug = RegOp.isDebug(); + + if (NonRegOp.isImm()) + RegOp.ChangeToImmediate(NonRegOp.getImm()); + else if (NonRegOp.isFI()) + RegOp.ChangeToFrameIndex(NonRegOp.getIndex()); + else return nullptr; - int64_t ImmVal = ImmOp.getImm(); - ImmOp.ChangeToRegister(RegOp.getReg(), false, false, - RegOp.isKill(), RegOp.isDead(), RegOp.isUndef(), - RegOp.isDebug()); - ImmOp.setSubReg(RegOp.getSubReg()); - RegOp.ChangeToImmediate(ImmVal); + NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug); + NonRegOp.setSubReg(SubReg); + return &MI; } diff --git a/llvm/test/CodeGen/AMDGPU/commute-compares.ll b/llvm/test/CodeGen/AMDGPU/commute-compares.ll index 731b47cd9ee..e21b694e4c4 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-compares.ll +++ b/llvm/test/CodeGen/AMDGPU/commute-compares.ll @@ -693,5 +693,20 @@ define void @commute_uno_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ret void } +; Without commuting the frame index in the pre-regalloc run of +; SIShrinkInstructions, this was using the VOP3 compare. + +; GCN-LABEL: {{^}}commute_frameindex: +; GCN: v_cmp_eq_i32_e32 vcc, 0, v{{[0-9]+}} +define void @commute_frameindex(i32 addrspace(1)* nocapture %out) #0 { +entry: + %stack0 = alloca i32 + %ptr0 = load volatile i32*, i32* addrspace(1)* undef + %eq = icmp eq i32* %ptr0, %stack0 + %ext = zext i1 %eq to i32 + store volatile i32 %ext, i32 addrspace(1)* %out + ret void +} + attributes #0 = { nounwind readnone } attributes #1 = { nounwind } |
